Methods and systems for detecting degradation of resistive memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsHan-sung JOO, Seung-You BAEK, Ki-sung KIM
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Abstract
A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.
Claims24
A method of operating a memory controller, the memory controller configured to control a resistive memory device, the resistive memory device including a plurality of memory cells, the method comprising:
- controlling the resistive memory device to program the plurality of memory cells to a first resistance state;
- controlling the resistive memory device to read the plurality of programmed memory cells;
- receiving, from the resistive memory device, a bit error rate (BER) of the memory cells generated during a read operation;
- and
- determining a quantity of program cycles of the memory cells based on the BER.
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A resistive memory device, comprising:
- a memory cell array including a plurality of memory cells;
- a write circuit configured to program the plurality of memory cells to a first resistance state;
- a read circuit configured to read the plurality of programmed memory cells;
- and
- a control circuitry configured to output, to an outside of the resistive memory device, a bit error rate (BER) of the memory cells generated during a read operation, to enable a quantity of program cycles of the plurality of memory cells to be determined based on the BER.
A memory system, comprising:
- a resistive memory device, the resistive memory device including
- a memory cell array including a plurality of memory cells,
- a write circuit configured to program the plurality of memory cells to a first resistance state,
- a read circuit configured to read the plurality of programmed memory cells, and
- a control circuitry configured to provide a bit error rate (BER) of the plurality of memory cells generated during a read operation;
- and
- a memory controller configured to control the resistive memory device,
- wherein
- the control circuitry is configured to provide the BER to the memory controller.
Dependencies are inferred from the claim text.