Semiconductor memory device and memory system

A semiconductor memory device comprising:

• a first memory cell array including a first memory cell;
• a second memory cell array including a second memory cell;
• a first word line electrically connected to a gate of the first memory cell;
• a second word line electrically connected to a gate of the second memory cell;
• a first bit line electrically connected to one end of the first memory cell;
• a second bit line electrically connected to one end of the second memory cell;
• a first sense amplifier electrically connected to the first bit line and configured to sense data read on the first bit line;
• and
• a second sense amplifier electrically connected to the second bit line and configured to sense data read on the second bit line;
• a first source line electrically connected to another end of the first memory cell;
• and
• a second source line electrically connected to another end of the second memory cell;
• and
• a control circuit configured to perform a read operation,
• wherein
• in the read operation,
• a first read voltage, a second read voltage and a third read voltage are sequentially applied to both the first word line and the second word line, the first to third read voltages being different from one another,
• a first source voltage and a second source voltage are applied to the first source line and the second source line, respectively, the first source voltage and the second source voltage being different from each other,
• the first sense amplifier reads data stored in the first memory cell through application of a first read voltage to the first word line, and
• the second sense amplifier reads data stored in the second memory cell upon through application of a second read voltage to the second word line and application of a third read voltage to the second word line.

A semiconductor memory device comprising:

• a first memory cell array including a first memory cell capable of storing two or more bits of data including at least a first bit and a second bit;
• a second memory cell array including a second memory cell capable of storing two or more bits of data including at least the first bit and the second bit;
• a first word line electrically connected to a gate of the first memory cell;
• a second word line electrically connected to a gate of the second memory cell;
• a first bit line electrically connected to one end of the first memory cell;
• a second bit line electrically connected to one end of the second memory cell;
• a first sense amplifier electrically connected to the first bit line and configured to:
• read the first bit of the data stored in the first memory cell upon receipt of a first control signal during application of a first read voltage to the first word line, and
• read the second bit of the data stored in the first memory cell upon receipt of the first control signal during application of a second read voltage to the first word line and application of a third read voltage to the first word line, the first to third read voltages being different from one another;
• a second sense amplifier electrically connected to the second bit line and configured to:
• read the first bit of the data stored in the second memory cell upon receipt of a second control signal during application of a fourth read voltage to the second word line, the first and fourth read voltages being substantially the same, and
• read the second bit of the data stored in the second memory cell upon receipt of the second control signal during application of a fifth read voltage to the second word line and application of a sixth read voltage to the second word line, the second and fifth read voltages being substantially the same, the third and sixth read voltages being substantially the same;
• and
• a control circuit configured to perform a read operation,
• wherein
• in the read operation,
• the first to third read voltages are sequentially applied to the first word line, and the fourth to sixth read voltages are sequentially applied to the second word line,
• the first sense amplifier reads the first bit of the data stored in the first memory cell upon receipt of the first control signal during application of the first read voltage to the first word line and the second read voltage to the second word line, and
• the second sense amplifier reads the second bit of the data stored in the second memory cell upon receipt of the second control signal during application of the second read voltage to the first word line, application of the third read voltage to the first word line, application of the fifth read voltage to the second word line, application of the sixth read voltage to the second word line.