Spram array
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy LIAW
Life of this patent
Estimating the term…
Abstract
SRAM arrays are provided. In each SRAM cell arranged in a column of cell array, a pull-down transistor and a pass-gate transistor are formed in P-type well region. A pull-up transistor is formed in N-type well region. At least one well strap cell includes an N-well strap structure formed on the N-type well region and a P-well strap structure formed on the P-type well region. A first distance between the active region of the P-well strap structure and the N-type well region is greater than a second distance between an active region of the pull-down transistor and the pass-gate transistor and the N-type well region.
Claims20
A Static Random Access Memory (SRAM) array, comprising:
- a plurality of SRAM cells arranged in a column of a cell array, each comprising:
- a pull-down transistor formed in a P-type well region of a substrate;
- a pull-up transistor formed in an N-type well region of the substrate;
- and
- a pass-gate transistor formed in the P-type well region;
- and
- at least one well strap cell arranged in the column of the cell array, comprising:
- an N-well strap structure formed on the N-type well region;
- and
- a P-well strap structure formed on the P-type well region and comprising an active region and P-type doping source and drain regions;
- wherein a first distance between the active region of the P-well strap structure and the N-type well region is greater than a second distance between an active region of the pull-down transistor and the pass-gate transistor and the N-type well region.
A Static Random Access Memory (SRAM) array, comprising:
- a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns of a cell array, wherein each of the SRAM cells arranged in the same column of the cell array comprises:
- a pull-down transistor formed in a P-type well region of a substrate;
- a pull-up transistor formed in an N-type well region of the substrate;
- and
- a pass-gate transistor formed in the P-type well region,
- wherein the pull-down transistor and the pass-gate transistor are single-fin N-type field effect transistors, and the pull-up transistor is single-fin P-type field effect transistor;
- and
- an N-well strap structure formed on the N-type well region;
- and
- a P-well strap structure formed on the P-type well region and comprising a fin and P-type doping source and drain regions on the fin;
- wherein in the same column of the cell array, a first distance between the fin of the P-well strap structure and the N-type well region is greater than a second distance between the N-type well region and a single fin shared by the pull-down transistor and the pass-gate transistor.
A Static Random Access Memory (SRAM) array, comprising:
- a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns of a cell array, wherein each of the SRAM cells arranged in the same column of the cell array comprises:
- a pull-down transistor formed in a P-type well region of a substrate;
- a pull-up transistor formed in an N-type well region of the substrate;
- and
- a pass-gate transistor formed in the P-type well region;
- and
- a plurality of well strap cells, wherein each of the well strap cells is arranged on one end of one of the columns in the cell array and comprises:
- an N-well strap structure formed on the N-type well region;
- a P-well strap structure formed on the P-type well region and comprising a fin and P-type doping source and drain regions on the fin;
- wherein in the P-type well regions of the two adjacent columns of the cell array, a first fin-to-fin distance between the fins of the P-well strap structures of the two adjacent well strap cells is less than a second fin-to-fin distance between single fins shared by the pull-down transistors and the pass-gate transistors of the two adjacent SRAM cells.
Dependencies are inferred from the claim text.