Semiconductor memory apparatus and refresh method of the semiconductor memory apparatus
AssigneeSK hynix Inc.
InventorNo Geun JOO
Life of this patent
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Abstract
A semiconductor memory apparatus includes a plurality of memory banks and a refresh control circuit. The refresh control circuit, in each plurality of cycles, performs a refresh operation on at least one memory bank of the plurality of memory banks at a first refresh rate, and performs a refresh operation on the other memory banks of the plurality of memory banks at a second refresh rate. The refresh control circuit circulates the at least one memory bank on which the refresh operation is performed at the first refresh rate in each one or more cycles of the plurality of cycles.
Claims30
A semiconductor memory apparatus comprising:
- a plurality of memory banks;
- and
- a refresh control circuit configured to, in each plurality of cycles, perform a refresh operation on at least one memory bank of the plurality of memory banks at a first refresh rate and perform a refresh operation on the other memory banks of the plurality of memory banks at a second refresh rate,
- wherein the refresh control circuit circulates the at least one memory bank on which the refresh operation is performed at the first refresh rate in each one or more cycles of the plurality of cycles.
A refresh method of a semiconductor memory apparatus which includes first and second memory banks each having at least four unit cell arrays, the refresh method comprising:
- Performing, during a first cycle, a refresh operation on a first unit cell array of the first memory bank, and performing a refresh operation on first and third unit cell arrays of the second memory bank;
- and
- performing, during a second cycle, a refresh operation on second and fourth unit cell arrays of the first memory bank, and performing a refresh operation on second unit cell array of the second memory bank.
A refresh method of a semiconductor memory apparatus which includes first, second, third, and fourth memory banks each having at least eight unit cell arrays, the refresh method comprising:
- performing, during a first cycle, a refresh operation on a first unit cell array of the first memory bank, and performing a refresh operation on first and fifth unit cell arrays of the second, third, and fourth memory banks;
- and
- performing, during a second cycle, a refresh operation on second unit cell arrays of the second memory bank, and performing a refresh operation on second and sixth unit cell arrays of the first, third, and fourth memory banks.
A refresh method of a semiconductor memory apparatus which includes first and fourth memory banks each having at least eight unit cell arrays, the refresh method comprising:
- performing, during a first cycle, a refresh operation on first unit cell arrays of the first and second memory banks, and performing a refresh operation on first and fifth unit cell arrays of the third and fourth memory banks;
- and
- performing, during a second cycle, a refresh operation on second unit cell arrays of the first and second memory banks, and performing a refresh operation on second and sixth unit cell arrays of the third and fourth memory banks.
Dependencies are inferred from the claim text.