Memory device, memory system, and method for refreshing memory device
AssigneeSK hynix Inc.
InventorHo Sung CHO
Life of this patent
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Abstract
A memory device applies different refresh rates to target data (or objective data) according to data characteristics (i.e., required reliability levels). The memory device includes a memory cell array provided with a plurality of memory cells, a row decoder configured to selectively activate word lines of the memory cell array in response to a row address signal, and a refresh controller configured to output the row address signal in response to the row address signal. The refresh controller controls a refresh ratio of a first storage region and a second storage region contained in the memory cell array in response to a changeable refresh control value.
Claims20
A memory device comprising:
- a memory cell array provided with a plurality of memory cells;
- a row decoder configured to selectively activate word lines of the memory cell array in response to a row address signal;
- and
- a refresh controller configured to output the row address signal in response to the row address signal,
- wherein the refresh controller controls a refresh ratio of a first storage region and a second storage region contained in the memory cell array based on a changeable refresh control value.
A memory system comprising:
- a memory device configured to store data in a first storage region and in a second storage region in response to a command signal and an address signal, and control a refresh ratio of the first storage region and the second storage region in response to a changeable refresh control value;
- and
- a memory controller configured to output the command signal, the address signal, and the refresh control value to the memory device in response to a control signal received from a host.
A method for refreshing a memory device comprising selectively outputting a first refresh address and a second refresh address in response to a refresh signal and a refresh control value,
- wherein the refresh control value is changeable, and a number of output times of the second refresh address is higher than a number of output times of the first refresh address by a predetermined number of times corresponding to a multiple of the refresh control value.
Dependencies are inferred from the claim text.