US 2020/0051613 A1Published application

Integrated Assemblies Comprising Supplemental Sense-Amplifier-Circuitry for Refresh

AssigneeMicron Technology, Inc.

InventorsScott J. Derner, Charles L. Ingalls

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Abstract

Some embodiments include an integrated assembly having a first memory array which includes a first column of first memory cells. A first digit line extends along the first column and is utilized to address the first memory cells of the first column. A second memory array is proximate to the first memory array and includes a second column of second memory cells. A second digit line extends along the second column and is utilized to address the second memory cells of the second column. A primary-sense-amplifier comparatively couples the first digit line with the second digit line. A first secondary-sense-amplifier is along the first digit line, and a second secondary-sense-amplifier is along the second digit line.

Claims20

Dependent claims

An integrated assembly, comprising:

a first memory array comprising a first column of first memory cells;
a first digit line extending along the first column of the first memory cells and being utilized to address the first memory cells of said first column;
a second memory array proximate to the first memory array and comprising a second column of second memory cells;
a second digit line extending along the second column of the second memory cells and being utilized to address the second memory cells of said second column;
a primary-sense-amplifier which comparatively couples the first digit line with the second digit line;
the primary-sense-amplifier being configured to be utilized during reading from and writing to the first and second memory cells along the first and second columns;
and
a first secondary-sense-amplifier along the first digit line, and a second secondary-sense-amplifier along the second digit line;
the first and second secondary-sense-amplifiers being configured to be utilized only to refresh the first and second memory cells along the first and second digit lines.

6 more elements

An integrated assembly, comprising:

a first memory array comprising a first column of first memory cells;
a first digit line extending along the first column of the first memory cells and being utilized to address the first memory cells of said first column;
a second memory array proximate to the first memory array and comprising a second column of second memory cells;
a second digit line extending along the second column of the second memory cells and being utilized to address the second memory cells of said second column;
a primary-sense-amplifier configured to comparatively couple the first digit line with the second digit line;
a first secondary-sense-amplifier along the first digit line, and a first switch between the first secondary-sense-amplifier and the first digit line;
the first switch being configured to be closed during a first operation along the first column to shunt an electrical signal past the first secondary-sense-amplifier;
the first switch being configured to be open during a second operation along the first column to enable the first secondary-sense-amplifier to comparatively couple a portion of the first digit line on one side of the first secondary-sense-amplifier with another portion of the first digit line on an opposing side of the first secondary-sense-amplifier;
and
a second secondary-sense-amplifier along the second digit line, and a second switch between the second secondary-sense-amplifier and the second digit line;
the second switch being configured to be closed during a first operation along the second column to shunt an electrical signal past the second secondary-sense-amplifier;
the second switch being configured to be open during a second operation along the second column to enable the second secondary-sense-amplifier to comparatively couple a portion of the second digit line on one side of the second secondary-sense-amplifier with another portion of the second digit line on an opposing side of the second secondary-sense-amplifier.

9 more elements

An integrated assembly, comprising:

a base;
a first deck over the base;
a second deck over the first deck;
a first memory array comprising a first column of first memory cells;
a first digit line extending along the first column of the first memory cells and being utilized to address the first memory cells of said first column;
a first portion of the first column of the first memory cells being along the first deck and a second portion of the first column of the first memory cells being along the second deck;
a second memory array proximate to the first memory array and comprising a second column of second memory cells;
a second digit line extending along the second column of the second memory cells and being utilized to address the second memory cells of said second column;
a first portion of the second column of the second memory cells being along the first deck and a second portion of the second column of the second memory cells being along the second deck;
a primary-sense-amplifier configured to comparatively couple the first digit line with the second digit line;
the primary-sense-amplifier being along the base;
a first secondary-sense-amplifier along the first digit line and coupled to the first digit line through a first transistor;
the first transistor having a first source/drain region coupled to a first portion of the first digit line, a second source/drain region coupled to a second portion of the first digit line, and a first gate coupled with an isolation driver;
and
a second secondary-sense-amplifier along the second digit line and coupled to the second digit line through a second transistor;
the second transistor having a third source/drain region coupled to a first portion of the second digit line, a second source/drain region coupled to a second portion of the second digit line, and a second gate coupled with the isolation driver.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/404,525Filed 6 May 2019
Priority: 9 Aug 2018
Published: 13 Feb 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 8/14
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out