Apparatus and methods for decoding memory access addresses for access operations

A memory, comprising:

• an array of memory cells comprising a plurality of blocks of memory cells;
• a plurality of driver circuitries, each driver circuitry of the plurality of driver circuitries connected to a respective block of memory cells of the plurality of blocks of memory cells;
• and
• block select circuitry having an output, wherein the output of the block select circuitry is selectively connected to each driver circuitry of the plurality of driver circuitries;
• wherein the plurality of driver circuitries is a first plurality of driver circuitries, and wherein the block select circuitry is a first block select circuitry, the memory further comprising:
• a second plurality of driver circuitries, each driver circuitry of the second plurality of driver circuitries connected to a respective block of memory cells of the plurality of blocks of memory cells;
• and
• a second block select circuitry having an output, wherein the output of the second block select circuitry is selectively connected to each driver circuitry of the second plurality of driver circuitries;
• wherein the output of the first block select circuitry is selectively connected to a first driver circuitry of the first plurality of driver circuitries in response to a first control signal;
• and
• wherein the output of the second block select circuitry is selectively connected to a first driver circuitry of the second plurality of driver circuitries in response to the first control signal.

A method of operating a memory, comprising:

• for each block of memory cells of a plurality of blocks of memory cells, determining whether that block of memory cells is selected for an access operation;
• generating a control signal having a first voltage level when at least one block of memory cells of the plurality of blocks of memory cells is selected for the access operation, and having a second voltage level, different than the first voltage level, when no block of memory cells of the plurality of blocks of memory cells is selected for the access operation;
• and
• for each block of memory cells of the plurality of blocks of memory cells, applying the control signal to driver circuitry for that block of memory cells when that block of memory cells is selected for the access operation.

A method of operating a memory, comprising:

• for each block of memory cells of a plurality of blocks of memory cells, determining whether that block of memory cells is selected for an access operation;
• generating a control signal having a first voltage level when at least one block of memory cells of the plurality of blocks of memory cells is selected for the access operation, and having a second voltage level, different than the first voltage level, when no block of memory cells of the plurality of blocks of memory cells is selected for the access operation;
• for each block of memory cells of the plurality of blocks of memory cells, applying the control signal to driver circuitry for that block of memory cells when that block of memory cells is selected for the access operation;
• and
• for a particular block of memory cells of the plurality of blocks of memory cells, sinking a current from driver circuitry for that block of memory cells to a current sink when the particular block of memory cells is not selected for the access operation.

A method of operating a memory, comprising:

• for each block of memory cells of a plurality of blocks of memory cells, determining whether that block of memory cells is selected for an access operation;
• generating a control signal having a first voltage level when at least one block of memory cells of the plurality of blocks of memory cells is selected for the access operation, and having a second voltage level, different than the first voltage level, when no block of memory cells of the plurality of blocks of memory cells is selected for the access operation;
• for each block of memory cells of the plurality of blocks of memory cells, applying the control signal to driver circuitry for that block of memory cells when that block of memory cells is selected for the access operation;
• and
• connecting local access lines of a particular block of memory cells of the plurality of blocks of memory cells to global access lines in response to applying the control signal to driver circuitry for the particular block of memory cells.

A method of operating a memory, comprising:

• for each block of memory cells of a plurality of blocks of memory cells, determining whether that block of memory cells is selected for an access operation;
• generating a control signal having a first voltage level when at least one block of memory cells of the plurality of blocks of memory cells is selected for the access operation, and having a second voltage level, different than the first voltage level, when no block of memory cells of the plurality of blocks of memory cells is selected for the access operation, and
• for each block of memory cells of the plurality of blocks of memory cells, applying the control signal to driver circuitry for that block of memory cells when that block of memory cells is selected for the access operation,
• wherein generating the control signal having the first voltage level comprises generating the control signal having a positive voltage level, and wherein generating the control signal having the second voltage level comprises generating the control signal having a negative voltage level.

A method of operating a memory, comprising:

• for each block of memory cells of a plurality of blocks of memory cells, determining whether that block of memory cells is selected for an access operation, wherein the plurality of blocks of memory cells comprises a plurality of subsets of blocks of memory cells, and wherein each block of memory cells of any subset of blocks of memory cells of the plurality of subsets of blocks of memory cells has a respective corresponding block of memory cells for each remaining subset of blocks of memory cells of the plurality of subsets of blocks of memory cells;
• and
• for each subset of blocks of memory cells of the plurality of subsets of blocks of memory cells:
• generating a respective control signal for that subset of blocks of memory cells having a first voltage level when at least one block of memory cells of that subset of blocks of memory cells is selected for the access operation, and having a second voltage level, different than the first voltage level, when no block of memory cells of that subset of blocks of memory cells is selected for the access operation;
• and
• for each block of memory cells of that subset of blocks of memory cells, applying the respective control signal for that subset of blocks of memory cells to driver circuitry for that block of memory cells when that block of memory cells, or its corresponding block of memory cells of any remaining subset of blocks of memory cells of the plurality of subsets of blocks of memory cells, is selected for the access operation.