Low-power source-synchronous signaling

An integrated circuit (IC) memory chip comprising:

• receiver circuitry to receive data signals from a memory controller and a first timing signal having a first phase relationship with the data signals, the receiver circuitry to receive a second timing signal, the second timing signal having a second phase relationship with the first timing signal;
• transmit circuitry to transmit feedback to the memory controller, the feedback based on a comparison between the first timing signal and an on-chip timing signal based on the second timing signal;
• and
• wherein an adjusted second timing signal is received by the receiver circuitry, the adjusted second timing signal exhibiting an updated second phase relationship relative to the first timing signal that is based on the transmitted feedback.

A method of operation in a memory device, the method comprising:

• receiving data signals from a memory controller and a first timing signal having a first phase relationship with the data signals;
• receiving a second timing signal having a second phase relationship with the first timing signal;
• transmitting feedback to the memory controller, the feedback based on a comparison between the first timing signal and an on-chip timing signal based on the second timing signal;
• and
• receiving an adjusted second timing signal, the adjusted second timing signal exhibiting an updated second phase relationship relative to the first timing signal that is based on the transmitted feedback.

A memory device comprising:

• receiver circuitry to receive data and a first timing signal from a memory controller, the first timing signal having a first phase relationship with the data, the receiver circuitry to receive a second timing signal from the memory controller, the second timing signal having a second phase relationship with the first timing signal;
• transmit circuitry to transmit feedback to the memory controller, the feedback based on a comparison between the first timing signal and an on-chip timing signal based on the second timing signal;
• and
• wherein an adjusted second timing signal is received by the receiver circuitry, the adjusted second timing signal exhibiting an updated second phase relationship relative to the first timing signal that is based on the transmitted feedback.