Memory device and image display apparatus including the same
AssigneeLG Electronics Inc.
InventorsHoshik KIM, Gwibeom HAN, Hoyeon HWANG
Life of this patent
Estimating the term…
Abstract
A memory device including a memory; a clock generator including a dual phase locked loop (PLL) and outputting a clock signal of the memory; and a memory controller configured to perform dynamic frequency scaling for changing a frequency of the clock signal of the memory based on the dual PLL. Further, phase detection is performed before the dynamic frequency scaling is started, and change the frequency of the clock signal of the memory during blocking of access to the memory according to the performance of the dynamic frequency scaling.
Claims20
A memory device comprising:
- a memory;
- a clock generator including a dual phase locked loop (PLL) and outputting a clock signal of the memory;
- and
- a memory controller configured to:
- perform dynamic frequency scaling for changing a frequency of the clock signal of the memory based on the dual PLL,
- wherein phase detection is performed before the dynamic frequency scaling is started, and
- change the frequency of the clock signal of the memory during blocking of access to the memory according to the performance of the dynamic frequency scaling.
A memory device comprising:
- a memory;
- a clock generator including a dual phase locked loop (PLL) and outputting a clock signal of the memory;
- and
- a memory controller configured to:
- perform dynamic frequency scaling for changing a frequency of the clock signal of the memory based on the dual PLL,
- wherein a maximum frequency of the frequency of the clock signal of the memory is not an integer multiple of a minimum frequency.
An image display apparatus comprising:
- a display;
- a controller;
- and
- a memory device,
- wherein the memory device comprising:
- a memory;
- a clock generator including a dual phase locked loop (PLL) and outputting a clock signal of the memory;
- and
- a memory controller configured to:
- perform dynamic frequency scaling for changing a frequency of the clock signal of the memory based on the dual PLL,
- wherein phase detection is performed before the dynamic frequency scaling is started, and
- change the frequency of clock signal of the memory during blocking of access to the memory according to the performance of the dynamic frequency scaling.
Dependencies are inferred from the claim text.