Sense amplifier with split capacitors

A method, comprising:

• coupling, during a read operation of a memory cell, a first capacitor with a voltage source and a node, the first capacitor in parallel with a second capacitor while coupled with the voltage source and the node;
• changing, after coupling the first capacitor with the voltage source and the node, a voltage of the voltage source to change a voltage of the node;
• coupling the memory cell with an access line while the node is coupled with the access line;
• decoupling the first capacitor from the node or the voltage source after coupling the memory cell with the access line;
• and
• determining, after decoupling the first capacitor, a value stored on the memory cell based at least in part on a voltage across the second capacitor.

An apparatus, comprising:

• a memory cell;
• a node configured to be selectively coupled with an access line of the memory cell during a read operation of the memory cell;
• a capacitive component coupled with a voltage source and the node, the capacitive component configured to provide a higher capacitance during a first portion of the read operation and a lower capacitance during a second portion of the read operation;
• a latch coupled with the node;
• and
• a controller configured to:
• increase a voltage of the voltage source during the first portion of the read operation;
• and
• activate the latch to determine a value stored on the memory cell after increasing the voltage of the voltage source.

An apparatus, comprising:

• a memory cell;
• a node configured to be selectively coupled with an access line of the memory cell during a read operation of the memory cell;
• a voltage source configured to be change voltage during the read operation;
• a capacitive component coupled with the node and the voltage source, the capacitive component configured to have a first capacitance during a first portion of the read operation and a second capacitance during a second portion of the read operation;
• and
• a latch coupled with the node and configured to determine a value stored on the memory cell based at least in part on a voltage of the node while the capacitive component has the second capacitance.