Apparatus and method of clock shaping for memory
AssigneeQUALCOMM Incorporated
InventorsMasoud ZAMANI, Bilal ZAFAR, Venkatasubramanian NARAYANAN
Life of this patent
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Abstract
A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.
Claims26
A clock delay and gating circuit comprising:
- a first AND gate coupled to a clock enable signal and a write enable signal;
- a first inverter coupled to the write enable signal;
- a second AND gate coupled to the clock enable signal and to the first inverter;
- a first clock gating cell coupled to a first clock signal and an output of the second AND gate;
- a second clock gating cell coupled to the first clock signal and an output of the first AND gate;
- a first inverter coupled to an output of the second clock gating cell;
- a second inverter coupled to an output of the first inverter;
- a third inverter coupled to an output of the second inverter;
- and
- an OR gate coupled to an output of the first clock gating cell and an output of the third inverter.
A clock delay and gating circuit comprising:
- first means for implementing a Boolean function coupled to a clock enable signal and a write enable signal;
- a first inverter coupled to the write enable signal;
- second means for implementing a Boolean function coupled to the clock enable signal and to the first inverter;
- a first means for gating a clock coupled to a first clock signal and an output of the second means for implementing a Boolean function;
- a second means for gating a clock coupled to the first clock signal and an output of the first means for implementing a Boolean function;
- a first inverter coupled to an output of the second means for gating a clock;
- a second inverter coupled to an output of the first inverter;
- a third inverter coupled to an output of the second inverter;
- and
- an OR gate coupled to an output of the first means for gating a clock and an output of the third inverter.
A memory circuit comprising:
- a first clock signal;
- a write enable signal, the write enable signal has a polarity;
- a clock delay circuit coupled to the first clock signal and the write enable signal, the clock delay circuit configured to output one of a second clock signal or a third clock signal based on the polarity of the write enable signal;
- and
- a memory coupled to the clock delay circuit.
A memory circuit comprising:
- a first clock signal;
- a write enable signal, the write enable signal has a polarity;
- means for delaying a clock coupled to the first clock signal and the write enable signal, the means for delaying a clock configured to output one of a second clock signal or a third clock signal based on the polarity of the write enable signal;
- and
- a memory coupled to the means for delaying a clock.
Dependencies are inferred from the claim text.