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US 2020/0051603 A1Published application
Clock signal drivers for read and write memory operations
AssigneeMicron Technology, Inc.
InventorsKatsuhiro Kitagawa, Akira Yamashita
Life of this patent
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Abstract
Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.
Claims20
A memory device, comprising:
- an input/output (I/O) circuit;
- a command input circuit;
- a first driver configured to generate a first set of clock signals provided to the command input circuit;
- and
- a second driver configured to generate a second set of clock signals provided to the I/O circuit.
2 more elements
A system, comprising:
- a memory array;
- an input/output (I/O) circuit associated with writing data into the memory array;
- a command input circuit associated with reading data from the memory array;
- a first driver configured to provide clock signals for the command input circuit;
- a second driver configured to provide clock signals for the I/O circuit;
- and
- circuitry configured to determine that data is not to be read from the memory array, and configured to adjust operation of the second driver to no longer provide the clock signals based on the determination that data is not to be read from the memory array.
4 more elements
A method, comprising:
- determining that read operations are to be performed related to a memory;
- providing first phase shifted clock signals from a first driver to a first circuit and second phase shifted clock signals from a second driver to a second circuit based on the determination that read operations are to be performed;
- determining that read operations are not to be performed;
- disabling the second driver based on the determination that read operations are not to be performed, disabling the second driver including not toggling the second phase shifted clock signals to no longer provide the second phase shifted clock signals;
- and
- providing the first phase shifted clock signals from the first driver to the first circuit for write operations.
3 more elements
Dependencies are inferred from the claim text.