Graphics architecture including a neural network pipeline

A graphics processing system comprising:

• a block of graphics compute units;
• a memory fetch unit coupled with the block of graphics compute units;
• and
• a programmable neural network unit including one or more neural network hardware blocks, wherein a neural network hardware block includes hardware logic to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by compute units within the block of graphics compute units.

An electronic device comprising:

• a block of graphics compute units;
• a graphics processor pipeline coupled to the block of graphics compute units;
• a programmable neural network unit including one or more neural network hardware blocks, the programmable neural network unit coupled with the block of graphics compute units and the graphics processor pipeline;
• and
• a tessellation module to configure the programmable neural network unit to generate tessellated output based on coarse input data.