Back to results
US 2020/0050930 A1Published application
Automated method and associated device for the non-volatile storage, retrieval and management of message/label associations and vice versa, with maximum likelihood
AssigneeAnother Brain
InventorPatrick PIRIM
Life of this patent
Estimating the term…
Abstract
An associative-memory-storage unit, and to an associative-memory-storage method are provided. The associative-memory-storage unit includes a first subset of at least memory sub-units over w bits, and a second memory sub-unit over v bits. The associative-memory-storage sub-unit may be used to associate messages with labels, and vice versa.
Claims52
An associative-memory-storage unit comprising:
- at least one first memory sub-unit (1_1 to 1_n) each comprising 2v words of w bits, the at least one first memory sub-unit forming a first set of n memory sub-units (n≥1);
- a second memory sub-unit comprising 2v words of v bits forming a second set;
- each memory sub-unit comprising:
- 2v memory positions for storing the words, each position being identified by a memory address over v bits;
- a v-bit memory-address input port (Adr);
- a v- or w-bit data input port (In);
- a v- or w-bit data output port (Out);
- a v-bit memory-address output port (Cadr);
- and
- a binary output (M) for validating the content;
- each memory sub-unit being configured:
- in a write mode, to store the word received via the data input port (In) at the address received via the memory-address input port (Adr);
- in a read mode:
- if one of the 2v memory positions contains the word received via the data input port (In), to validate the binary output signal (M) for validating the present content, and to deliver the address of the position to the memory-address output port (Cadr);
- otherwise, to not validate the binary output signal (M) for validating the content.
12 more elements
A method for associative memory storage by an associative-memory-storage unit, comprising:
- at least one first memory sub-unit (1_1 to 1_n) each comprising 2v words of w bits, said at least one first memory sub-unit forming a first set of n memory sub-units (n≥1);
- a second memory sub-unit comprising 2v words of v bits forming a second set;
- each memory sub-unit comprising:
- 2v memory positions for storing the words, each position being identified by a memory address over v bits;
- a v-bit memory-address input port (Adr);
- a v- or w-bit data input port (In);
- a v- or w-bit data output port (Out);
- a v-bit memory-address output port (Cadr);
- and
- a binary output (M) for validating the content;
- said method comprising:
- in a write mode, storing the word received via the data input port (In) at the address received via the memory-address input port (Adr);
- in a read mode:
- if one of the 2v memory positions contains the word received via the data input port (In), validating the binary output signal (M) for validating the present content, and delivering the address of the position to the memory-address output port (Cadr);
- otherwise, not validating the binary output signal (M) for validating the content.
12 more elements
The associative-memory-storage method as claimed in claim 31, comprising:
- activating a first bus (AB) of the associative-memory unit in read and write mode;
- activating a second bus of the associative-memory unit, independently of the first, in read mode.
Dependencies are inferred from the claim text.