Multiplication and addition device for matrices, neural network computing device, and method

A method for neural network operations, comprising:

• selecting, by a submatrix divider circuit, a portion of an input data matrix as an input submatrix;
• receiving, by a matrix element memory, a convolution kernel matrix that includes one or more kernel values, wherein each of the one or more kernel values is represented as a sequence that includes one or more bits;
• respectively storing, by the matrix element memory, the one or more bits in one or more storage spaces in accordance with positions of the one or more bits in the sequence;
• calculating, by a calculator circuit, an intermediate result for each storage space based on one or more input elements in the input submatrix, wherein the one or more input elements correspond to non-zero values stored in the storage space;
• summing, by an accumulator circuit, the intermediate results to generate an output value;
• and
• assembling, by a convolution result assembler circuit, the output values calculated for different portions of the input data matrix to generate an output matrix.

An electronic device, comprising a chip that includes a neural network operation device, the neural network operation device comprising:

• a submatrix divider circuit configured to select a portion of an input data matrix as an input submatrix;
• a matrix element memory configured to:
• receive a convolution kernel matrix that includes one or more kernel values, wherein each of the one or more kernel values is represented as a sequence that includes one or more bits, and
• respectively store the one or more bits in one or more storage spaces in accordance with positions of the one or more bits in the sequence;
• a calculator circuit configured to calculate an intermediate result for each storage space based on one or more input elements in the input submatrix, wherein the one or more input elements correspond to non-zero values stored in the storage space;
• an accumulator circuit configured to sum the intermediate results to generate an output value;
• and
• a convolution result assembler circuit configured to assemble the output values calculated for different portions of the input data matrix to generate an output matrix.