US 2020/0050734 A1Published application

Apparatuses having diversified logic circuits and methods thereof

AssigneeNXP B.V.

InventorJan-Peter Schat

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Abstract

An example apparatus includes application circuit that carries out a specific set of actions on an input data vector, and a decoding circuit. The application circuit includes: a first diversification logic circuit that processes data corresponding to the input data vector and in response, generates a coded first output data vector; and a second diversification logic circuit that processes the data corresponding to the input data vector and in response, generate a coded second output data vector, the coded second output data vector being uniquely coded relative to the coded first output data vector. The decoding circuit assesses the coded first output data vector relative to the coded second output data vector and, in response, generates output data indicative of a likelihood of a design weakness in the application circuit.

Claims20

Dependent claims

An apparatus comprising:

an application circuit configured and arranged to carry out a specific set of actions on an input data vector, the application circuit having a plurality of coded-diversification pathways including:
a first diversification logic circuit configured and arranged to process data corresponding to the input data vector and in response, generate a coded first output data vector;
and
a second diversification logic circuit configured and arranged to process data corresponding to the input data vector and in response, generate a coded second output data vector, the coded second output data vector being uniquely coded relative to the coded first output data vector;
and
a decoding circuit including a decoder configured as a function of the second diversification logic circuit, the decoding circuit configured and arranged to assess the coded first output data vector relative to the coded second output data vector and, in response, generate output data indicative of a likelihood of a design weakness in the application circuit.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/057,106Filed 7 Aug 2018
Published: 13 Feb 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3312
Using simulation: timing analysis
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation