Re-routing time critical multi-sink nets in chip design
AssigneeInternational Business Machines Corporation
InventorLUKAS DAELLENBACH
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AssigneeInternational Business Machines Corporation
InventorLUKAS DAELLENBACH
Estimating the term…
A method for improving a routing of a single chip multi-sink net of a semiconductor circuit may be provided. The method includes receiving a netlist describing at least one routed multi-sink net and timing information related to a signal propagation delay between a source and individual sinks. The method also includes determining a timing slack value related to a routed path from the source to the individual sinks and determining at least one critical sink out of the individual sinks based on the related timing slack value, wherein the critical sink has a related timing slack value that is larger than a predefined threshold value. The method additionally includes deleting all routed wires of the multi-sink net, and rerouting the multi-sink net, wherein at least one subnet of the multi-sink net, comprising the source and the critical sink, is routed before routing the remaining individual sinks of the multi-sink net.
A computer-implemented method for improving a routing of a single chip multi-sink net of a semiconductor circuit, the method comprising:
A routing system for improving a routing of a single chip multi-sink net of a semiconductor circuit, the system comprising:
A computer program product for improving a routing of a single chip multi-sink net of a semiconductor circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by one or more computing systems or controllers to cause the one or more computing systems to:
Dependencies are inferred from the claim text.