Method for coloring circuit layout and system for performing the same

A lithography method, comprising:

• receiving a multiple-patterning technology (MPT)-compliant circuit layout having a plurality of nodes, each node representing a circuit pattern;
• identifying nodes being separated by a distance less than a minimum separation distance as target networks, the target networks being presented in an imaginary X-Y coordinate plane;
• using a coordinate-based method to identify a first node in each target network;
• assigning a first color to the first node in each target network;
• assigning the first color and a second color to remaining nodes in the target networks in an alternating manner so that any two immediately adjacent nodes in the target network have different colors;
• assigning the nodes assigned with the first color to a first photomask and manufacturing the first photomask;
• assigning the nodes assigned with the second color to a second photomask and manufacturing the second photomask;
• and
• performing a lithography process to pattern a substrate using the first and second photomasks.

A lithography process system, comprising:

• a non-transitory computer-readable memory storing a program and a design rule checker;
• and
• a processor operatively coupled with the memory,
• wherein the program, when executed by the processor, causes the processor to receive data from a design rule checker to:
• identify a first node in a G0-linked network using a coordinate-based method, the G0-linked network being presented in an imaginary X-Y coordinate plane in the computer;
• assign a first feature to the identified first node in the G0-linked network;
• and
• assign the first feature and a second feature to remaining nodes in the G0-linked network in an alternating manner so that any two immediately adjacent linked nodes in the G0-linked network have different features.