Flexible protocol and associated hardware for one-wire radio frequency front-end interface

An apparatus, comprising:

• an interface circuit adapted to couple the apparatus to a datalink;
• and
• a protocol controller configured to:
• transmit a one-bit sequence start condition (SSC) over a data wire of the datalink, the SSC having a first edge that commences a pulse-width modulated datagram and a second edge that indicates an optimal sampling point in each bit period of the pulse-width modulated datagram;
• provide a command field in the pulse-width modulated datagram, wherein a first-transmitted bit of the command field identifies the pulse-width modulated datagram as a write command directed to a register located at address zero;
• provide data in a third-transmitted bit and subsequently-transmitted bits of the command field to be written to the register located at address zero when a second-transmitted bit of the command field has a first value;
• and
• provide a payload field comprising data to be written to a register located at an address provided in the third-transmitted bit and the subsequently-transmitted bits of the command field when the second-transmitted bit of the command field has a second value.

An apparatus comprising:

• means for transmitting a one-bit sequence start condition (SSC) over a data wire of a datalink, the SSC having a first edge that commences a pulse-width modulated datagram and a second edge that indicates an optimal sampling point in each bit period of the pulse-width modulated datagram;
• and
• means for providing fields in the pulse-width modulated datagram, including a command field that comprises a first-transmitted bit of the command field identifying the pulse-width modulated datagram as a write command directed to a register located at address zero,
• wherein data is provided in a third-transmitted bit and subsequently-transmitted bits of the command field to be written to the register located at address zero when a second-transmitted bit of the command field has a first value, and
• wherein data is provided in a payload field comprising the data to be written to a register located at an address provided in the third-transmitted bit and the subsequently-transmitted bits of the command field when the second-transmitted bit of the command field has a second value.

A processor-readable storage medium comprising code for:

• transmitting a one-bit sequence start condition (SSC) over a data wire of a datalink, the SSC having a first edge that commences transmission of a pulse-width modulated datagram and a second edge that indicates an optimal sampling point in each bit period of the pulse-width modulated datagram;
• providing a command field in the pulse-width modulated datagram, wherein a first-transmitted bit of the command field identifies the pulse-width modulated datagram as a write command directed to a register located at address zero;
• providing data in a third-transmitted bit and subsequently-transmitted bits of the command field to be written to the register located at address zero when a second-transmitted bit of the command field has a first value;
• and
• providing a payload field comprising data to be written to a register located at an address provided in the third-transmitted bit and the subsequently-transmitted bits of the command field when the second-transmitted bit of the command field has a second value.