Solid state device with distributed bit buckets

A data storage apparatus comprising:

• a non-volatile memory (NVM);
• and
• a controller coupled to the NVM, the controller comprising:
• a processor;
• a memory coupled to the processor, wherein the memory comprises a plurality of addresses, the plurality of addresses configured to store dummy data;
• and
• a first hardware engine coupled to the processor and the memory, the first hardware engine comprising a first internal memory, wherein the first hardware engine is configured to:
• receive a first read request for data stored at a first address of the memory;
• determine whether the first address is an address from the plurality of addresses of the memory;
• when the first address is amongst the plurality of addresses, provide a first response comprising a particular data stored at the first internal memory, without retrieving data stored at the first address of the memory;
• and
• when the first address is not amongst the plurality of addresses, (i) retrieve the data stored at the first address of the memory, and (ii) provide a first response comprising the data retrieved from the first address of the memory.

A method for operating a data storage apparatus, comprising:

• receiving a first read request for data stored at a first address of a memory of the data storage apparatus;
• determining whether the first address is an address from a plurality of addresses of the memory;
• when the first address is amongst the plurality of addresses, providing a first response comprising a particular data, without retrieving data stored at the first address of the memory;
• and
• when the first address is not amongst the plurality of addresses, (i) retrieving data stored at the first address of the memory, and (ii) providing a first response comprising the data retrieved from the first address of the memory.

An apparatus comprising:

• means for non-volatile storing of data;
• and
• means for controlling the means for non-volatile storing of data, comprising:
• means for processing data;
• means for storing data comprising a plurality of addresses, the means for storing data coupled to the means for processing data, wherein the plurality of addresses is configurable to have different numbers of addresses;
• and
• means for direct memory access (DMA) coupled to the means for storing data and the means for processing data, wherein the means for DMA is configured to:
• receive a first read request for data stored at a first address of the memory;
• determine whether the first address is an address from the plurality of addresses of the memory;
• when the first address is amongst the plurality of addresses, provide a first response comprising a particular data, without retrieving data stored at the first address of the means for storing data, wherein the particular data that is included with the first response is different than the data that is stored at the first address of the means for storing data;
• and
• when the first address is not amongst the plurality of addresses, (i) retrieve data stored at the first address of the means for storing data, and (ii) provide a first response comprising the data retrieved from the first address of the means for storing data.

A controller comprising:

• a processor;
• a memory coupled to the processor, the memory comprising a plurality of addresses, wherein the plurality of addresses is programmable such that a subset of addresses from the plurality of addresses, is configured to be used as a bit bucket;
• and
• a direct memory access (DMA) circuitry coupled to the processor and the memory, wherein the DMA circuitry is configured to:
• receive a first read request for data stored at a first address of the memory;
• determine whether the first address is an address from the subset of addresses of the memory;
• when the first address is amongst the subset of addresses, provide a first response comprising a particular data, without retrieving data stored at the first address of the memory;
• and
• when the first address is not amongst the subset of addresses, (i) retrieve the data stored at the first address of the memory, and (ii) provide a first response comprising the data retrieved from the first address of the memory.