Pattern Processor

A pattern processor, comprising a single-crystalline semiconductor substrate, an input bus for transferring at least a first portion of a first pattern, and a plurality of storage-processing units (SPU's) communicatively coupled with said input bus, each of said SPU's comprising:

• at least a three-dimensional non-volatile memory (3D-NVM) array including memory cells for storing at least a second portion of a second pattern, wherein said memory cells are neither in contact with nor interposed therebetween by any semiconductor substrate including said single-crystalline semiconductor substrate;
• and, said memory cells do not comprise any single-crystalline semiconductor material;
• a pattern-processing circuit and at least a portion of a peripheral circuit of said 3D-NVM array disposed on said single-crystalline semiconductor substrate, wherein said pattern-processing circuit performs pattern processing for said first and second patterns;
• said peripheral circuit is communicatively coupled with said pattern-processing circuit;
• and, said pattern-processing circuit and said portion of said peripheral circuit comprise at least a single-crystalline semiconductor material;
• a plurality of inter-storage-processor (ISP) connections for communicatively coupling said memory cells and said peripheral circuit, wherein said ISP-connections do not penetrate through any semiconductor substrate including said single-crystalline semiconductor substrate;
• and, said memory cells and said pattern-processing circuit at least partially overlap.

A searchable storage, comprising an input bus for transferring at least a search pattern and a plurality of searchable 3-D memories communicatively coupled with said input bus, each of said searchable 3-D memories comprising a single-crystalline semiconductor substrate and a plurality of storage-processing units (SPU's) communicatively coupled with said input bus, each of said SPU's comprising:

• at least a three-dimensional non-volatile memory (3D-NVM) array including memory cells for storing at least a portion of data, wherein said memory cells are neither in contact with nor interposed therebetween by any semiconductor substrate including said single-crystalline semiconductor substrate;
• and, said memory cells do not comprise any single-crystalline semiconductor material;
• a pattern-processing circuit and at least a portion of a peripheral circuit of said 3D-NVM array disposed on said single-crystalline semiconductor substrate, wherein said pattern-processing circuit performs pattern processing for said search pattern and said portion of data;
• said peripheral circuit is communicatively coupled with said pattern-processing circuit;
• and, said pattern-processing circuit and said portion of said peripheral circuit comprise at least a single-crystalline semiconductor material;
• a plurality of inter-storage-processor (ISP) connections for communicatively coupling said memory cells and said peripheral circuit, wherein said ISP-connections do not penetrate through any semiconductor substrate including said single-crystalline semiconductor substrate;
• and, said memory cells and said pattern-processing circuit at least partially overlap;
• whereby the primary purpose of said searchable storage is long-term data storage and the secondary purpose of said searchable storage is in-situ search.