Apparatuses and methods including memory commands for semiconductor memories

An apparatus, comprising:

• a memory configured to receive a timing command and an associated access command, wherein the timing command is configured to enable a clock signal synchronization option and to set a delay for when an input buffer is disabled following the associated access command when the clock signal synchronization option is enabled, wherein responsive to the timing command, the memory configured to synchronize a data clock signal and internal clock signals generated therefrom and further configured to delay when the input buffer is disabled based on a delay set by the timing command.

An apparatus, comprising:

• a controller configured to provide a timing command and an associated access command to a memory, wherein the timing command is configured to enable a clock signal synchronization option and to set a delay for when an input buffer of the memory is disabled following an access command associated with the timing command when the clock signal synchronization option is enabled, the controller further configured to provide a data clock signal to the input buffer of the memory to be synchronized by the memory.