Interface for memory readout from a memory component in the event of fault
AssigneeRambus Inc.
InventorsFrederick A. Ware, Kenneth L. Wright
Life of this patent
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Abstract
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
Claims21
(canceled)
A method of operation in an integrated circuit (IC) memory component having a memory core, the method comprising:
- accessing the memory core during a normal mode of operation with a primary interface including data input/output (I/O) circuitry and control/address (C/A) input circuitry;
- detecting a fault with an error code;
- initiating a fault mode of operation in response to the detected fault;
- and
- accessing the memory core during the fault mode of operation with a secondary interface.
A method of operation in a memory module, the memory module including a primary databus connector and multiple IC memory components coupled to the primary databus connector via respective primary interfaces, the memory module including a secondary data bus coupled to respective secondary interfaces of the multiple IC memory components, each IC memory component including a memory core, wherein the method comprising:
- for each of the multiple IC memory components,
- accessing the memory core during a normal mode of operation with a corresponding primary interface;
- detecting a fault with an error code;
- initiating a fault mode of operation in response to the detected fault;
- and
- accessing the memory core during the fault mode of operation with a corresponding secondary interface.
A method of operation in a memory system, the memory system including a primary databus connector and multiple IC memory components coupled to the primary databus connector via respective primary interfaces, the memory module including a secondary data bus coupled to respective secondary interfaces of the multiple IC memory components, each IC memory component including a memory core, wherein the method comprising:
- for each of the multiple IC memory components,
- accessing the memory core during a normal mode of operation with a corresponding primary interface;
- detecting a fault with an error code;
- initiating a fault mode of operation in response to the detected fault;
- and
- accessing the memory core during the fault mode of operation with a corresponding secondary interface.
Dependencies are inferred from the claim text.