Apparatus for Data Processing, Artificial Intelligence Chip and Electronic Device
AssigneeBeijing Baidu Netcom Science Technology Co., Ltd.
InventorsPeng Wu, Jian Ouyang, Canghai Gu, Wei Qi, Ningyi Xu
Life of this patent
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Abstract
Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.
Claims19
An apparatus for data processing, comprising:
- at least one input memory, the input memory configured to store to-be-processed data;
- at least one data conveying component, the data conveying component configured to read an external processing instruction, parse the processing instruction to acquire a read data address, a write data address, and an operating command, read the to-be-processed data from the at least one input memory based on the read data address, process the to-be-processed data based on the operating command to obtain output data and a corresponding write data address after multiplexed processing, and send a write data request;
- at least one multiplexed arbitration component, the multiplexed arbitration component configured to receive, in response to receiving the write data request of the at least one data conveying component, the output data and the corresponding write data address of the at least one data conveying component, select output data and a corresponding write data address of one of the at least one data conveying component from the received output data and write data address, output the selected output data and corresponding write data address, and send a write enable signal;
- and
- at least one output memory, configured to receive, in response to receiving the write enable signal sent by the multiplexed arbitration component, the output data and the corresponding write data address from the multiplexed arbitration component, and write the received output data into the corresponding write data address.
An artificial intelligent chip, comprising an apparatus for data processing, the apparatus comprising:
- at least one input memory, the input memory configured to store to-be-processed data;
- at least one data conveying component, the data conveying component configured to read an external processing instruction, parse the processing instruction to acquire a read data address, a write data address, and an operating command, read the to-be-processed data from the at least one input memory based on the read data address, process the to-be-processed data based on the operating command to obtain output data and a corresponding write data address after multiplexed processing, and send a write data request;
- at least one multiplexed arbitration component, the multiplexed arbitration component configured to receive, in response to receiving the write data request of the at least one data conveying component, the output data and the corresponding write data address of the at least one data conveying component, select output data and a corresponding write data address of one of the at least one data conveying component from the received output data and write data address, output the selected output data and corresponding write data address, and send a write enable signal;
- and
- at least one output memory, configured to receive, in response to receiving the write enable signal sent by the multiplexed arbitration component, the output data and the corresponding write data address from the multiplexed arbitration component, and write the received output data into the corresponding write data address.
Dependencies are inferred from the claim text.