Mram noise mitigation for write operations with simultaneous background operations

A method of writing data into a memory device, the method comprising:

• utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank;
• writing a second plurality of data words and associated memory addresses into an error buffer, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the error buffer is associated with the memory bank and wherein further the second plurality of data words comprises data words that are awaiting write verification associated with the memory bank;
• searching for two data words that are awaiting write verification in the error buffer, wherein verify operations associated with the two data words are operable to be performed in a same cycle as a write operation, and wherein the verify operations associated with the two data words occur in a same row as the write operation;
• determining if an address associated with any of the two data words is adjacent to an address for the write operation;
• and
• de-prioritizing a verify operation associated with any of the two data words if a corresponding address for the verify operation is adjacent to the write operation, wherein the verify operation is scheduled to occur in a different cycle than the write operation.

A memory device for storing data, the memory device comprising:

• a memory bank comprising a plurality of addressable memory cells;
• a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank;
• a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the cache memory is associated with the memory bank and wherein further the second plurality of data words comprises data words that are awaiting write verification associated with the memory bank;
• and
• a logic module operable to:
• search for three data words that are awaiting write verification in the error buffer, wherein verify operations associated with the three data words are operable to be performed in a same cycle as a write operation, and wherein the verify operations associated with the three data words occur in a same row as the write operation;
• determining if an address associated with any of the three data words is adjacent to an address for the write operation;
• and
• de-prioritizing a verify operation associated with any of the three data words if a corresponding address for the verify operation is adjacent to an address of the write operation.