Information processing apparatus, non-transitory computer-readable recording medium having information processing program stored thereon, and method of processing information

A non-transitory computer-readable recording medium having an information processing program stored thereon, for causing a computer comprising a memory, and a processor coupled to the memory, to execute a process comprising:

• determine a bit mode in which a first program associated with a first instruction to be executed by the processor, operates;
• when the determined bit mode is a third bit mode of a first bit mode, a second bit mode, and the third bit mode, the first bit mode specifying a bit length of addresses in the memory to a first bit length, the second bit mode specifying the bit length to a second bit length greater than the first bit length, the third bit mode specifying the bit length to a third bit length greater than the second bit length, set information indicating that the third bit mode is enabled, to a second setting area in a storing region, the storing region comprising a first setting area to which a value indicating either one of the first bit mode and the second bit mode is set, the second setting area to which the information indicating whether the third bit mode is enabled or disabled is set, and an address area to which an address in the first bit length or the second bit length is set;
• set a concatenated address to the first setting area and the address area;
• and
• access the memory based on the concatenated address defined by concatenating the value set in the first setting area and the address set in the address area.

A method of processing information in an information processing apparatus comprising a memory, and a processor coupled to the memory, the method comprising, by the processor:

• determining, whether or not information set in a second setting area in a first storing region indicates that a third bit mode is enabled, the first storing region comprising:
• a first setting area to which a value indicating either one of a first bit mode and a second bit mode is set, the first bit mode specifying a bit length of addresses in the memory to a first bit length, the second bit mode specifying the bit length to a second bit length greater than the first bit length;
• the second setting area to which the information indicating whether the third bit mode is enabled or disabled is set, the third bit mode specifying the bit length to a third bit length greater than the second bit length;
• and
• an address area to which an address in the first bit length or the second bit length is set;
• and
• when the information set in the second setting area indicates that the third bit mode is enabled, accessing the memory based on a concatenated address defined by concatenating the value set in the first setting area and the address set in the address area.