Accelerator validation and reporting

An apparatus comprising:

• at least one processor;
• a memory coupled to the at least one processor;
• first and second Field Programmable Gate Array (FPGAs) that each comprises an Open Coherent Accelerator Processor Interface (OpenCAPI);
• and
• an accelerator manager residing in the memory and executed by the at least one processor, the accelerator manager validating an accelerator image by:
• deploying the accelerator image to a first programmable device to provide a first accelerator;
• running the first accelerator to generate first results;
• simulating an accelerator design corresponding to the accelerator image;
• running the simulated accelerator design to generate second results;
• comparing the first results to the second results;
• when the first results match the second results, providing a first validation indication;
• deploying the accelerator image to the second programmable device to provide a second accelerator;
• running the second accelerator to generate third results;
• comparing the first results to the third results;
• when the first results match the third results, providing a second validation indication;
• deploying the accelerator image to a cloud of an accelerator provider that provided the accelerator image to provide a third accelerator;
• running a plurality of tests on the third accelerator to determine whether a plurality of specifications are met;
• when the plurality of specifications are met, providing a third validation indication;
• and
• when the accelerator manager provides the first, second and third validation indications, the accelerator manager indicating the accelerator image is valid.