Computing Method Applied to Artificial Intelligence Chip, and Artificial Intelligence Chip

An artificial intelligent chip, comprising:

• at least one processor core;
• a computational accelerator connected to each of the at least one processor core;
• and
• a storage apparatus, storing at least one program thereon, wherein the at least one program, when executed by the artificial intelligence chip, causes the artificial intelligence chip to implement operations, the operations comprising:
• decoding, by a target processor core among the at least one processor core, a to-be-executed instruction to obtain a computational identifier and at least one operand;
• generating, by the target processor core, a complex computational instruction using the computational identifier and the at least one operand obtained by the decoding, in response to determining that the computational identifier obtained by decoding is a preset complex computational identifier;
• adding, by the target processor core, the generated complex computational instruction to a complex computational instruction queue;
• selecting, by the computational accelerator, a complex computational instruction from the complex computational instruction queue;
• executing, by the computational accelerator, a complex computation indicated by the complex computational identifier in the selected complex computational instruction using at least one operand in the selected complex computational instruction as an inputted parameter, to obtain a computational result;
• and
• writing, by the computational accelerator, the obtained computational result as a complex computational result into a complex computational result queue.

A non-transitory computer readable medium, storing a computer program thereon, wherein the program, when executed by an artificial intelligence chip, implements operations, the operations comprising:

• decoding, by a target processor core among at least one processor core, a to-be-executed instruction to obtain a computational identifier and at least one operand;
• generating, by the target processor core, a complex computational instruction using the computational identifier and the at least one operand obtained by the decoding, in response to determining that the computational identifier obtained by decoding is a preset complex computational identifier;
• adding, by the target processor core, the generated complex computational instruction to a complex computational instruction queue;
• selecting, by the computational accelerator, a complex computational instruction from the complex computational instruction queue;
• executing, by the computational accelerator, a complex computation indicated by the complex computational identifier in the selected complex computational instruction using at least one operand in the selected complex computational instruction as an inputted parameter, to obtain a computational result;
• and
• writing, by the computational accelerator, the obtained computational result as a complex computational result into a complex computational result queue.