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US 2020/0050471 A1Published application
Detecting bus locking conditions and avoiding bus locks
AssigneeIntel Corporation
InventorsVedvyas Shanbhogue, Gilbert Neiger, Arumugam Thiyagarajah
Life of this patent
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Abstract
A processor may include a register to store a bus-lock-disable bit and an execution unit to execute instructions. The execution unit may receive an instruction that includes a memory access request. The execution may further determine that the memory access request requires acquiring a bus lock, and, responsive to detecting that the bus-lock-disable bit indicates that bus locks are disabled, signal a fault to an operating system.
Claims21
(canceled)
A processor comprising:
- a register to store a bus-lock-disable bit, wherein the register comprises an architectural model-specific register (MSR) visible from outside of the processor;
- and
- an execution unit to execute instructions, wherein the execution unit is to:
- receive an instruction that includes a memory access request;
- determine that the memory access request requires acquiring a bus lock;
- and
- responsive to detecting that the bus-lock-disable bit indicates that bus locks are disabled, signal a fault to an operating system.
4 more elements
A method comprising:
- receiving, by execution unit of a processor, an instruction that generates a memory access request;
- determining, by the execution unit, that the memory access request requires acquiring a bus lock;
- and
- responsive to determining that a bus-lock-disable bit is enabled within a register, transmitting, by the execution unit, a fault to an operating system executed by the processor, wherein the register comprises an architectural model-specific register (MSR) visible from outside of the processor.
1 more element
A system comprising:
- a register to store a bus-lock-disable bit, wherein the register comprises an architectural model-specific register (MSR) visible from outside of the processor;
- and
- an execution unit to execute instructions, wherein the execution unit is to:
- receive an instruction that includes a memory access request;
- determine that the memory access request requires acquiring a bus lock;
- and
- responsive to detecting that the bus-lock-disable bit indicates that bus locks are enabled, enable acquisition of the bus lock before execution of the memory access request.
4 more elements
Dependencies are inferred from the claim text.