Method for Processing Information, and Processor
AssigneeBeijing Baidu Netcom Science Technology Co., Ltd.
InventorJian Ouyang
Life of this patent
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Abstract
Embodiments of the present disclosure relate to a method for processing information, and a processor. The processor includes an arithmetic and logic unit, a bypass unit, a queue unit, a multiplexer, and a register file. The bypass unit includes a data processing subunit; the data processing subunit is configured to acquire at least one valid processing result outputted by the arithmetic and logic unit, determine a processing result from the at least one valid processing result, output the determined processing result to the multiplexer, and output processing results except for the determined processing result of among the at least one valid processing result to the queue unit; and the multiplexer is configured to sequentially output more than one valid processing results to the register file.
Claims17
A processor, comprising an arithmetic and logic unit, a bypass unit, a queue unit, a multiplexer, and a register file, the bypass unit comprising a data processing subunit;
- wherein the data processing subunit is configured to acquire at least one valid processing result outputted by the arithmetic and logic unit, determine a processing result from the at least one valid processing result, output the determined processing result to the multiplexer, and output processing results except for the determined processing result among the at least one valid processing result to the queue unit, the processing result comprising an enable signal, the valid processing result comprising a high-level enable signal or a low-level enable signal;
- and
- the multiplexer is configured to sequentially output more than one valid processing results to the register file, the more than one valid processing results comprising the determined processing result and a valid processing result outputted from the queue unit.
A method for processing information applied to a processor, the processor comprising an arithmetic and logic unit, a bypass unit, a queue unit, a multiplexer, and a register file, the bypass unit comprising a data processing subunit;
- the method comprising:
- acquiring, by the data processing subunit, at least one valid processing result outputted by the arithmetic and logic unit, determining a processing result from the at least one valid processing result, outputting the determined processing result to the multiplexer, and outputting processing results except for the determined processing result of among the at least one valid processing result to the queue unit, the processing result comprising an enable signal, the valid processing result comprising a high-level enable signal or a low-level enable signal;
- and
- sequentially outputting, by the multiplexer, more than one valid processing results to the register file, the more than one valid processing results comprising the determined processing result and a valid processing result outputted from the queue unit.
Dependencies are inferred from the claim text.