US 2020/0050393 A1 · MEMORIES FOR READING DATA CORRESPONDING TO MULTIPLE ADDRESSES ASSOCIATED WITH A READ COMMAND

Abstract

Memories, and systems incorporating similar memories, as well as their operation, where the memory might include an array of memory cells, a status register, and a controller configured to access the array of memory cells. The controller may further be configured to perform a plurality of read operations on the array of memory cells in response to a read command associated with a plurality of addresses, store a particular value to the status register in response to data of a particular read operation corresponding to a particular address of the plurality of addresses being available for readout by an external device, and store a different value to the status register in response to data of a different read operation corresponding to a different address of the plurality of addresses being available for readout by the external device.

Claims25

Dependent claims

A memory, comprising:

an array of memory cells;
a status register;
and
a controller configured to access the array of memory cells;
wherein the controller is further configured to:
perform a plurality of read operations on the array of memory cells in response to a read command associated with a plurality of addresses, each read operation of the plurality of read operations corresponding to a respective address of the plurality of addresses;
in response to data of a particular read operation of the plurality of read operations corresponding to a particular address of the plurality of addresses being available for readout by an external device, storing a particular value to the status register;
and
in response to data of a different read operation of the plurality of read operations corresponding to a different address of the plurality of addresses being available for readout by the external device, storing a different value to the status register.

6 more elements

An electronic system, comprising:

a processor;
and
a memory in communication with the processor;
wherein the processor is configured to:
issue a read command to the memory, wherein the read command is associated with N addresses, and wherein N is an integer value greater than one;
read a status register of the memory until the status register indicates that data corresponding to a particular address of the N addresses is available for readout;
when the status register indicates that the data corresponding to the particular address is available for readout, read out that data from the memory;
determine a next address of the N addresses;
read the status register of the memory until the status register indicates that data corresponding to the next address is available for readout;
and
when the status register indicates that the data corresponding to the next address is available for readout, read out that data from the memory;
and
wherein the memory is configured to:
store a particular value to the status register to indicate that the data corresponding to the particular address is available for readout;
and
store a different value to the status register to indicate that the data corresponding to the next address is available for readout.

13 more elements

Dependencies are inferred from the claim text.

Memories for reading data corresponding to multiple addresses associated with a read command

Life of this patent

Memories for reading data corresponding to multiple addresses associated with a read command

Life of this patent

Abstract

Claims25