Active matrix substrate and liquid crystal display device

2:

• The active matrix substrate according to claim 1,
• wherein each of the plurality of pixels further has a contact hole that is formed in the interlayer insulating layer and the inorganic insulating layer and reaches a drain extension section extending from the first drain electrode.

3:

• The active matrix substrate according to claim 2,
• wherein an angle of a side surface of the contact hole to a surface parallel to the substrate is smaller than an angle of the side surface of the at least one recess to the surface parallel to the substrate.

4:

• The active matrix substrate according to claim 2, further comprising an upper metal layer that is in direct contact with the first transparent conductive layer or the second transparent conductive layer and that contains metal,
• wherein the upper metal layer includes a first portion covering the at least one recess when viewed in a normal direction of the substrate.

5:

• The active matrix substrate according to claim 4,
• wherein the upper metal layer further includes a second portion covering a channel region of a semiconductor layer of the first TFT when viewed in a normal direction of the substrate.

6:

• The active matrix substrate according to claim 4,
• wherein the upper metal layer is in direct contact with the first transparent conductive layer and does not overlap the contact hole when viewed in a normal direction of the substrate.

8:

• The active matrix substrate according to claim 7,
• wherein each of the plurality of pixels further has a third portion that is included in the lower metal layer, and is electrically connected to the auxiliary capacitor electrode, and
• wherein the at least one recess further includes a hole formed in the gate insulating layer and a hole formed in the lower insulating layer, and reaches the third portion.

10:

• The active matrix substrate according to claim 9,
• wherein the lower metal layer further includes a lower light shielding section formed to cover at least a channel region of the second semiconductor layer when viewed in a normal direction of the substrate.

11:

• The active matrix substrate according to claim 9,
• wherein the plurality of first TFTs have a first semiconductor layer formed on the gate insulating layer, the first semiconductor layer includes an oxide semiconductor, and the second semiconductor layer includes crystalline silicon.

12:

• The active matrix substrate according to claim 1,
• wherein the at least one recess is formed adjacent to the first TFT in each of the plurality of pixels.

13:

• The active matrix substrate according to claim 1,
• wherein the interlayer insulating layer includes an organic insulating layer having a thickness of 1 μm to 4 μm.

14:

• The active matrix substrate according to claim 1,
• wherein the angle of the side surface of the at least one recess to the surface parallel to the substrate is 70° or more.

15:

• The active matrix substrate according to claim 1,
• wherein the at least one recess further includes a hole formed in the gate insulating layer.

16:

• The active matrix substrate according to claim 1,
• wherein two pixels, out of the plurality of pixels, adjacent to each other in the second direction are associated with source bus lines, out of the plurality of source bus lines, different from each other.

18:

• The liquid crystal display device according to claim 17,
• wherein the second transparent electrode functions as a pixel electrode, and the counter substrate has a counter electrode opposite the second transparent electrode.

19:

• The liquid crystal display device according to claim 17,
• wherein the second transparent electrode has at least one slit, the second transparent electrode functions as a pixel electrode, and the first transparent electrode functions as a common electrode.