Semiconductor devices including stacked dies and methods of testing the semiconductor devices

A semiconductor device, comprising:

• a buffer die;
• and
• first through Nth stack dies stacked on the buffer die and configured to communicate with the buffer die via through electrodes (where N is an integer equal to or greater than 2),
• wherein the buffer die comprises a delay control circuit configured to receive and delay test inputs for testing the first through Nth stack dies from an external test logic, and output the delayed test inputs, in a test mode of the semiconductor device,
• wherein, based on a delay amount set in the delay control circuit, a timing at which the test inputs are transmitted to some of the first through Nth stack dies is different from a timing at which the test inputs are transmitted to the others of the first through Nth stack dies.

A test method of a semiconductor device comprising a buffer die and a plurality of stacked dies stacked thereon, the test method comprising:

• receiving, in a test mode of the semiconductor device, by the buffer die, test inputs for testing the plurality of stack dies from an external test logic;
• delaying, by a delay control circuit provided in the buffer die, the test inputs according to delay amounts set in response to a delay control signal;
• transferring, by the buffer die, the delayed test inputs to the plurality of stack dies via through electrodes;
• and
• performing, by the plurality of stacked dies, test signal processing by using the test inputs,
• wherein a test execution timing of some of the plurality of stack dies is different from the test execution timing of the other of the plurality of stack dies.