Scan test method and apparatus
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.
Claims19
An integrated circuit comprising:
- (a) a first scan register having a first scan data input, a first scan data output, a scan clock input and a scan enable input;
- (b) a second scan register having a second scan data input, a second scan data output, a scan clock input and a scan enable input;
- (c) compactor circuitry having an input coupled to the first scan data output, an input coupled to the second scan data output, and a test data output;
- (d) test access circuitry having a test clock input, a test mode select input, a scan clock output coupled to the scan clock inputs of the first and second scan registers, and a control output;
- and
- (e) gating circuitry having a control input coupled to the control output, and a scan enable output coupled to the scan enable inputs of the first and second scan registers.
An integrated circuit comprising:
- (a) decompressor circuitry having a single, compressed scan data input, a scan clock input, a scan enable input, a first decompressed scan data output, and a second decompressed scan data output;
- (b) a first scan register having a first scan data input coupled to the first decompressed scan data output, a scan clock input, a scan enable input, and a first scan data output;
- (c) a second scan register having a second scan data input coupled to the second decompressed scan data output, a scan clock input, a scan enable input, and a second scan data output;
- (d) compactor circuitry having a first scan data input coupled to the first scan data output, a second scan data input coupled to the second scan data output and a single compacted scan data output;
- (e) test access circuitry having a test clock input, a test mode select input, a scan clock output coupled to the scan clock inputs of the decompressor circuitry, the first scan register, and the second scan register, and a control output;
- and
- (f) gating circuitry having a control input coupled to the control output, and a scan enable output coupled to the scan enable inputs of the decompressor circuitry, the first scan register, and the second scan register.
Dependencies are inferred from the claim text.