Device and methods for reducing peak noise and peak power consumption in semiconductor devices under test

A test device, comprising:

• a device under test (DUT) mounting circuit on which a plurality of semiconductor devices are mounted as a DUT;
• and
• a test logic configured to generate a test input provided to target circuits in the plurality of semiconductor devices and determine whether the DUT is defective based on a test output from the plurality of semiconductor devices,
• wherein the test logic is configured to provide the test input to the plurality of semiconductor devices in parallel, and
• wherein a timing at which the test input is delivered to target circuits in some of the plurality of semiconductor devices is different from a timing at which the test input is delivered to target circuits in some other semiconductor devices.

A semiconductor device comprising:

• a delay control circuit configured to receive a test input provided from an external test logic in a test mode, delay the test input, and output a delayed test input;
• and
• a target circuit configured to receive the delayed test input from the delay control circuit,
• wherein the delay control circuit is configured to delay the test input depending on a delay amount set in response to a delay control signal in the test mode.