Cycle accurate and cycle reproducible memory for an fpga based hardware accelerator

A system for simulating operations of an integrated circuit device under test (DUT) to validate the DUT, the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, the system comprising:

• a plurality of target Field Programmable Gate Arrays (FPGAs);
• a plurality of target memories communicatively associated with the FPGAs, each of the target memories having a second number of input ports, and operating in target clock cycles at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd;
• and
• a simulation control for simulating operation of the DUT by, in said defined cycle of time, applying the given set of inputs to the target memories via the input ports of the target memories to simulate operation of the DUT, wherein in said defined cycle of time, each of the target memories has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memories has an associated state, the simulation control including
• a global control to initiate and stop the simulation on the target FPGAs, and
• a plurality of local controls to forward system commands from the global control to the target FPGAs, each of the local controls being associated with one or more of the target FPGAs to forward the system commands from the global control to said one or more of the target FPGAs to maintain cycle accuracy between the device memory and the target memories, wherein at the end of said defined cycle of time, the device memory and the target memories are in the same state to validate the DUT over the defined cycle of time.

An article of manufacture comprising:

• at least one tangible computer readable hardware device having computer readable program code logic tangibly embodied therein to simulate operations of an integrated circuit device under test (DUT) to validate the DUT using a plurality of Field Programmable Gate Arrays (FPGAs), and to maintain cycle accurate memories for the FPGAs, the DUT including a device memory having a first number of input ports and operating in device clock cycles at a frequency Fd, each of the FPGAs being associated with a target memory having a second number of input ports and operating in target clock signals at a frequency Ft, said second number being less than said first number, and Ft being greater than Fd, the computer readable program code logic, when executing, performing the following:
• in a defined cycle of time, applying a given set of inputs to the device memory via the input ports of the device memory, and
• simulating operation of the DUT by, in said defined cycle of time, applying the given set of inputs to the target memories via the input ports of the target memories to simulate operation of the DUT, wherein in said defined cycle of time, each of the target memories has more target clock cycles than the device memory has device clock cycles, and at an end of said defined cycle of time, each of the device memory and the target memories has an associated state, including
• using a global control to initiate and stop the simulation on the target FPGAs, and
• using a plurality of local controls to forward system commands from the global control to the target FPGAs, each of the local controls being associated with one or more of the target FPGAs to forward the system commands from the global control to said one or more of the target FPGAs to maintain cycle accuracy between the device memory and the target memories, wherein at the end of said defined cycle of time, the device memory and the target memories are in the same state to validate the DUT over the defined cycle of time.