Control area network (can) bus fault detection
AssigneeTexas Instruments Incorporated
InventorsRichard Edwin HUBBARD, Abhijeeth AAREY PREMANATH, Terry MAYHUGH, Mark Edward WENTROBLE, Wesley Ryan RAY
Life of this patent
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Abstract
A CAN bus transceiver includes CAN bus fault detection circuitry that can provide detailed information to simplify the task of the service technician when there is a CAN bus fault. Voltage and current measurements of the CAN bus are made and from them a fault type is determined. A time-domain reflectometer monitors the CAN bus signals for transmitted and reflected signals and from them a distance to the fault is determined. Either or both values are provided to a service technician to allow error determination and correction.
Claims19
A control area network (CAN) bus integrated circuit comprising:
- CAN bus high and low pins;
- a CAN bus high drive transistor coupled to the CAN bus high pin;
- a CAN bus low driver transistor coupled to the CAN bus low pin;
- an amplifier coupled to the CAN bus high and low pins and providing a CAN bus differential voltage signal as an output;
- a set of voltmeter comparators receiving the CAN bus differential voltage signal and including a plurality of comparators, to monitor the CAN bus differential voltage signal and provide a plurality of output signals, each output signal indicating a different voltage level of the CAN bus differential voltage signal is present;
- a P amplifier connected to the CAN bus high drive transistor to determine current through the CAN bus high drive transistor;
- an N amplifier connected to the CAN bus low drive transistor to determine current through the CAN bus low drive transistor;
- a summer coupled to the P amplifier and the N amplifier to subtract the current through the CAN bus low drive transistor from the current through the CAN bus high drive transistor to develop a CAN bus drive current;
- a set of current meter comparators coupled to the summer and including a plurality of comparators, to monitor the CAN bus drive current and provide a plurality of outputs signals, each output signal indicating a different drive current level of the CAN bus is present;
- and
- a decoder coupled to the set of voltmeter comparators output signals and the set of current meter comparators output signals to decode the set of voltmeter comparators and the set of current meter comparators output signals to provide a fault code output.
A control area network (CAN) bus integrated circuit comprising:
- CAN bus high and low pins;
- a transmit data signal pin;
- an amplifier coupled to the CAN bus high and low pins and providing a CAN bus differential voltage signal as an output;
- a differentiator coupled to the amplifier to determine leading edges of signals on the CAN bus from the CAN bus differential voltage signal;
- a driven signal integrator coupled to the differentiator to determine a valid driven signal leading edge on the CAN bus and provide an output to indicate the valid driven signal leading edge;
- a reflected signal integrator coupled to the differentiator to determine a valid reflected signal leading edge on the CAN bus and provide an output to indicate the valid reflected signal leading edge;
- and
- a timer coupled to the driven signal integrator and the reflected signal integrator and to the transmit data signal pin to time the difference between the valid driven signal leading edge and the valid reflected signal leading edge and provide a digital output time value of the difference.
The CAN bus integrated circuit of claim 9, wherein the timer further includes a plurality of flip-flops coupled to the plurality of delay elements, each flip-flop receiving a data input from a respective delay element, each flip-flop clocked by the valid reflected signal leading edge indication. ii. The CAN bus integrated circuit of claim 10, wherein the timer further includes a plurality of AND gates coupled to the plurality of flip-flops, each AND gate receiving one input from a respective flip-flop and all but the last AND gate receiving one input from the next flip-flop.
The CAN bus integrated circuit of claim n, wherein the timer further includes a gray encoder coupled to the plurality of AND gates to convert the outputs of the plurality of AND gates into a gray code.
A control area network (CAN) bus integrated circuit comprising:
- CAN bus high and low pins;
- a transmit data signal pin;
- a CAN bus high drive transistor coupled to the CAN bus high pin;
- a CAN bus low driver transistor coupled to the CAN bus low pin;
- an amplifier coupled to the CAN bus high and low pins and providing a CAN bus differential voltage signal as an output;
- a set of voltmeter comparators receiving the CAN bus differential voltage signal and including a plurality of comparators, to monitor the CAN bus differential voltage signal and provide a plurality of outputs signals, each output signal indicating a different voltage level of the CAN bus differential voltage signal is present;
- a P amplifier connected to the CAN bus high drive transistor to determine current through the CAN bus high drive transistor;
- an N amplifier connected to the CAN bus low drive transistor to determine current through the CAN bus low drive transistor;
- a summer coupled to the P amplifier and the N amplifier to subtract the current through the CAN bus low drive transistor from the current through the CAN bus high drive transistor to develop a CAN bus drive current;
- a set of current meter comparators coupled to the summer and including a plurality of comparators, to monitor the CAN bus drive current and provide a plurality of outputs signals, each output signal indicating a different drive current level of the CAN bus is present;
- a decoder coupled to the set of voltmeter comparators output signals and the set of current meter comparators output signals to decode the set of voltmeter comparators and the set of current meter comparators output signals to provide a fault code output;
- a differentiator coupled to the amplifier to determine leading edges of signals on the CAN bus from the CAN bus differential voltage signal;
- a driven signal integrator coupled to the differentiator to determine a valid driven signal leading edge on the CAN bus and provide an output to indicate the valid driven signal leading edge;
- a reflected signal integrator coupled to the differentiator to determine a valid reflected signal leading edge on the CAN bus and provide an output to indicate the valid reflected signal leading edge;
- and
- a timer coupled to the driven signal integrator and the reflected signal integrator and to the transmit data signal pin to time the difference between the valid driven signal leading edge and the valid reflected signal leading edge and provide a digital output time value of the difference.
Dependencies are inferred from the claim text.