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AssigneeSony Semiconductor Solutions Corporation
InventorsMasahiro SATO, Machiko KAMETANI, Jun OGI, Yuri KATO
Estimating the term…
The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing deterioration in signal characteristics due to parasitic capacitance caused by providing a configuration for realizing an electrode plating process when an electrode and an amplifier are provided on the same substrate. When a power source supplies a potential necessary for plating processing and a breaker reads a signal from liquid, and an amplifier amplifies and outputs the signal, the power source required for the plating processing is blocked with respect to the electrode. This is applicable to the potential measuring apparatus.
A semiconductor apparatus comprising:
A potential measuring apparatus comprising:
Dependencies are inferred from the claim text.
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Processes for servicing or operating cells for electrolytic coating: process control or regulation
By investigating electrochemical variables; by using electrolysis or electrophoresis: association of two or more measuring systems or cells, each…
Electrolytic cell components: electrodes, e.g. test electrodes; Half-cells
Electrodes, e.g. test electrodes; Half-cells: reference electrodes
Term end not estimated
The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus, and more particularly, to a semiconductor apparatus and a potential measuring apparatus capable of preventing electrostatic breakdown during manufacturing.
In recent years, a technology for measuring an action potential of nerve cells and contributing medical research regarding the nerve action has been required. For example, an electrode apparatus for measuring and recording the action potential of the nerve cells has been proposed (refer to Patent Documents 1 and 2).
Patent Document 1: Japanese Patent Application Laid-Open No. 06-078889 Patent Document 2: Japanese Patent Application Laid-Open No. 2002-031617
FIG. 1 is a diagram for explaining an exemplary configuration of a general potential measuring apparatus.
FIG. 2 is a diagram for explaining an exemplary configuration of a potential measuring apparatus according to the present disclosure.
FIG. 3 is a diagram for explaining an exemplary configuration of the potential measuring apparatus in FIG. 2.
Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that, in the present specification and the drawings, components having substantially the same functional configuration are denoted with the same reference numeral so as to omit redundant description.
<Exemplary Configuration of General Potential Measuring Apparatus>
In description of a potential measuring apparatus according to the present disclosure, first, an exemplary configuration of a general potential measuring apparatus will be described with reference to FIG. 1. An upper part of FIG. 1 is a schematic perspective diagram of a potential measuring apparatus 1, a middle part of FIG. 1 is a wiring diagram corresponding to a top view of a petri dish 11 and an electrode substrate 12, and a lower part of FIG. 1 is a wiring diagram of a side cross section of the potential measuring unit 1.