Enhanced plating bath and additive chemistries for cobalt plating

#Implementations of the present disclosure generally relate to the fabrication and cobalt metallization of integrated circuits using, for example, single and dual Damascene processes.

#Microelectronic devices, such as micro-scale electronic, electro-mechanical or optical devices are generally fabricated on and/or in work pieces or substrates, such as silicon wafers. In a typical fabrication process, for example on a semiconductor material wafer, a conductive seed layer is first applied onto the surface of the substrate using chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating processes, or other suitable methods. After forming the seed layer, a layer of metal is plated onto the substrate by applying an appropriate electrical potential between the seed layer and one or more electrodes in the presence of an electro-processing solution containing metal ions. The substrate is then cleaned and/or annealed in subsequent procedures to form devices, contacts or conductive lines. Some substrates may have a barrier layer with the seed layer formed on the barrier layer.

#Currently, most microelectronic devices are made on substrates plated with copper (Cu). Although copper has high conductivity, it typically involves a barrier layer such as tantalum nitride (TaN) to prevent diffusion of copper into the substrate or dielectric material on the substrate. These types of barrier layers have relatively low conductivity. Using known techniques, features on the substrate are filled with electroplated copper using acidic copper electroplating solutions. These electroplating solutions often use additives to promote a super-conformal fill process (with the features filling primarily from the bottom up, rather than inwardly from the sides) to create a void-free fill. As the feature sizes shrink, achieving void-free fill with the traditional copper plating processes has become more difficult. In addition, as the features get smaller, the barrier layer used for copper occupies a larger relative volume of the smaller feature, because a minimum barrier layer thickness is typically necessary to prevent copper diffusion, regardless of feature size.

#So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical implementations of the disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.

#FIGS. 1A-1C is a cross-sectional view of a cobalt plating scheme according to one implementation of this disclosure.

#FIGS. 2A-2C is a cross-sectional view of a prior art cobalt plating scheme.

#To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one implementation may be beneficially utilized on other implementations without specific recitation. The drawings referred to here should not be understood as being drawn to scale unless specifically noted. In addition, the drawings are often simplified and details or components omitted for clarity of presentation and explanation. The drawings and discussion serve to explain principles discussed below, where like designations denote like elements.

#Implementations of the disclosure are directed to methods for cobalt electroplating and metallization of features in a semiconductor device, such as the trenches and vias formed by single or dual Damascene processes. Damascene process electroplating baths contain “additive packages” or “additive systems,” wherein a combination of additives in certain ratios facilitates the metal filling of high aspect ratio sub-micrometer features, preferably with a low-defect density and a preferred grain structure.

#Certain mixtures of additives in an additive package may promote the bottom-up filling of high aspect ratio interconnect features (such as trenches and vias) in a phenomena known as super-filling. During super-filling, the rate of metal deposition is accelerated at the bottom of the feature, while the rate of plating at the sidewalls of the feature and the top entry is suppressed or slowed. In this fashion, the trench may be filled up with a metal without being prematurely sealed off or “pinched off” by plated metal at the top of the opening, and void defects may be avoided.