Processing circuitry

A multiplication circuit for multiplying a first input value by a second input value comprising:

• a first signal path configured to receive a first signal with a value corresponding to the sum of the first input value and second input value and to generate a first output value which is a function of the square of the value of the first signal;
• a second signal path configured to receive a second signal with a value corresponding to the difference between the first input value and the second input value and to generate a second output value which is a function of the square of the value of the second signal;
• and
• a subtractor for determining a difference between the first output value and second output value;
• wherein each of the first and second signal paths comprises a self-oscillating time-encoding modulator and a time-decoding converter.

A processing circuit comprising:

• a signal combiner configured to receive first and second input signals and to generate a first combined signal corresponding to a sum of the first and second input signals and a second combined signal corresponding to a difference between the first and second input signals;
• first and second time-encoding modulators configured to receive the first and second combined signals respectively and generate respective first and second cyclic signals with a cycle frequency, wherein the cycle frequency is substantially proportional to (1−R2) where R is a value of the respective input to the respective time-encoding modulator normalised within a range of −1 to +1 with respect to an input range of the time-encoding modulator;
• and
• first and second counters configured to receive the first and second cyclic signals respectively and produce first and second count values;
• and
• a subtractor configured to determine a difference between the first and second count values.