# US 2020/0041564 A1 · Apparatus and Method for Testing Semiconductor Devices

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- Number: US 2020/0041564 A1
- Document ID: US20200041564A1
- Status: Published application
- Kind: A1
- Application number: 16/532,388
- Filed: 2019-08-05
- Published: 2020-02-06
- Earliest claimed: 2018-08-06
- Assignees: Testmetrix, Inc.
- Applicants: Testmetrix, Inc.
- Inventors: Christian O. Cojocneanu; Lucian Scurtu
- Web page: https://patentgrep.com/patent/US20200041564A1

## CPC

- G01R 31/2868: {Complete testing stations; systems; procedures; software aspects}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/275: {for testing individual semiconductor components within integrated circuits}
- G01R 31/2867: {Handlers or transport devices, e.g. loaders, carriers, trays}
- G01R 31/2887: {involving moving the probe head or the IC under test; docking stations (moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392)}
- G01R 31/2889: {Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence)}
- G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)}
- H05K 7/20272: {Accessories for moving fluid, for expanding fluid, for connecting fluid conduits, for distributing fluid, for removing gas or for preventing leakage, e.g. pumps, tanks or manifolds}
- G01R 1/0491: {for testing integrated circuits on wafers, e.g. wafer-level test cartridge}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

The invention is a test system for testing silicon wafers or packaged devices. The system includes a tester having multiple testing stacks that each hold a vertical stack of test engines, data buffers, pin drivers, and other resources, which are electrically connected on one side to a wafer or DUT and on the other side to a test host computer via fast data links. Each testing stack is disposed on a top side of a wafer contactor electrically connected to a wafer or a load board electrically connected to a DUT. The system includes a cooling system to remove heat during operation. The system minimizes the data signal path between the pads of the devices being tested and the pin drivers of the tester, the test engines, and the test host computer. High performance is possible by the connection of bottom of each testing stack directly to the wafer contactor.

## Claims

### Claim 1

A device for testing a silicon wafer, comprising:
a plurality of vertical stacks of test boards, wherein each of said test boards are electrically connected to a host computer;
a corresponding plurality of electrical connectors, each electrically connected to each of said test boards in a corresponding one of said vertical stacks of test boards and disposed at the bottom of said corresponding one of said vertical stacks of test boards;
a plate having a top side and a bottom side, wherein each of said plurality of vertical stacks of test boards and corresponding plurality of electrical connectors is disposed on said top side of said plate, wherein said plate comprises an electrical trace between each of said corresponding plurality of electrical connectors to a corresponding location on said bottom side of said plate for electrical connection to a silicon wafer under test.