Processor array redundancy
AssigneeMIPS Tech, LLC
InventorsMajid Bemanian, Lawrence H Hudepohl
Life of this patent
Estimating the term…
Loading patent…
AssigneeMIPS Tech, LLC
InventorsMajid Bemanian, Lawrence H Hudepohl
Estimating the term…
Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.
A processor-implemented method for data validation comprising:
(canceled)
11-12. (canceled)
(canceled)
17-19. (canceled)
23-25. (canceled)
28-32. (canceled)
37-39. (canceled)
A computer program product embodied in a non-transitory computer readable medium for data validation, the computer program product comprising code which causes one or more processors to perform operations of:
A computer system for data validation comprising:
Dependencies are inferred from the claim text.