Zero offset clock distribution

A network transmitting device, comprising:

• a plurality of processing blocks, each of the plurality of processing blocks receiving a corresponding plurality of clock signals,
• wherein a first processing block of the plurality of processing blocks generates an output clock signal based on a first clock signal of the plurality of clock signals,
• wherein each of the plurality of processing blocks except the first processing block compares a frequency of the first clock signal with a frequency of the corresponding one of the plurality of clock signals to generate frequency offset data,
• wherein each of the plurality of processing blocks except the first processing block generates phase offset data comparing the corresponding one of the plurality of clock signals with the first clock signal over a specific time, and
• wherein the first processing block encodes the frequency offset data and the phase offset data onto the output clock signal.

A network receiving device, comprising:

• a first processing block that receives an input signal from a network receiving device, the input signal including a first clock signal, encoded frequency offset data, and encoded phase offset data, wherein the first processing block recovers the first clock signal and retrieves the encoded frequency offset data and the encoded phase offset data;
• and
• one or more second processing blocks coupled to the first processing block, the one or more second processing blocks receiving the first clock signal and the frequency offset data from the first processing block,
• wherein the one or more second processing blocks generates a frequency offset adjustment based on a comparison of the phase offset data received with the input signal and receiver phase offset data generated in the one or more second processing blocks, and
• wherein the one or more second processing blocks recover a corresponding clock signal from the first clock signal, the frequency offset data, and the frequency offset adjustment.