Processor and information processing apparatus

An information processing apparatus comprising:

• a memory;
• a memory control circuit connected to the memory by a first communication line group and a second communication line group and the memory control circuit configured to:
• measure an error rate of a signal that propagates through a communication line included in each of the first communication line group and the second communication line group;
• switch to use a spare line to perform a first communication with the memory when a first error rate of a signal that propagates through a first communication line included in the first communication line group exceeds a first threshold value, the first communication being a communication performed using the first communication line;
• and
• switch to use the first communication line to perform the first communication and switch to use the spare line to perform a second communication with the memory when the first communication is performed using the spare line, when a second error rate of a signal that propagates through a second communication line included in the second communication line group exceeds a second threshold value higher than the first threshold value, and when the first error rate is lower than the second threshold value, the second communication being a communication performed using the second communication line;
• and
• a processor core configured to exchange information with the memory via the memory control circuit.