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US 2020/0028720 A1Published application
Multi-level signaling in memory with wide system interface
AssigneeMicron Technology, Inc.
InventorsTimothy M. Hollis, Markus Balb, Ralf Ebert
Life of this patent
Estimating the term…
Abstract
Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
Claims21
(canceled)
An apparatus, comprising:
- an array of memory cells;
- a controller configured to control operation of memory cells in the array of memory cells;
- an interposer formed of a first material and operatively coupled with the array of memory cells and the controller, wherein the interposer comprises a plurality of channels between the array of memory cells and the controller;
- a substrate coupled with the interposer and formed of a second material different than the first material;
- and
- a receiver configured to determine a logic state represented by a signal modulated using a first modulation scheme communicated across at least one channel of the interposer.
3 more elements
A method, comprising:
- identifying, by a controller of a memory device, information to be written to an array of memory cells;
- generating, by the controller, a signal that represents a plurality of bits of the identified information, wherein the signal is modulated using a first modulation scheme;
- and
- transmitting, by the controller, the signal to the array of memory cells across an interposer that comprises a plurality of channels, wherein the interposer is formed of a first material and coupled with a substrate formed of a second material different than the first material.
1 more element
An apparatus, comprising:
- an array of memory cells;
- an interposer formed of a first material and operatively coupled with the array of memory cells, wherein the interposer comprises a plurality of channels;
- a substrate coupled with the interposer and formed of a second material different than the first material;
- and
- a controller operatively coupled with the interposer, the controller configured to:
- identify information to be written to the array of memory cells;
- generate a signal that represents a plurality of bits of the identified information, wherein the signal is modulated using a first modulation scheme;
- and
- transmit the signal to the array of memory cells across the interposer.
6 more elements
Dependencies are inferred from the claim text.