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US 2020/0028515 A1Published application
Compact phase-locked loop with low jitter and reference spurs
AssigneeThe Trustees of Columbia University in the City of New York
InventorsShravan Siddartha Nagam, Peter R. Kinget
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Abstract
The present disclosure relates to a phase-locked loop (PLL) including a frequency detector, a sub-sampling phase detector (SSPD), and a voltage-controlled oscillator (VCO). The frequency detector is configured to receive a reference signal and an output signal, and to generate a coarse-tuning voltage that indicates a frequency difference between the reference signal and the output signal. The SSPD is configured to sub-sample the output signal using the reference signal, and to generate a fine-tuning voltage that indicates a phase difference between the reference signal and the output signal. The VCO is configured to update the output signal based on the coarse-tuning voltage and the fine-tuning voltage.
Claims21
A phase-locked loop (PLL) comprising:
- a frequency divider, which is configured to receive an output signal and generate a divided signal by frequency dividing the output signal with a frequency divide ratio;
- a frequency detector, which is configured to receive a reference signal and the divided signal, and generate a coarse-tuning voltage, wherein the coarse-tuning voltage indicates a frequency difference between the reference signal and the divided signal;
- a controlled slope buffer configured to receive the divided signal and generate a buffered divided signal, wherein:
- the buffered divided signal and the divided signal have a same frequency;
- and
- the buffered divided signal has a higher slope and shorter rising time than the divided signal;
- a sub-sampling phase detector (SSPD), which is configured to sub-sample the buffered divided signal using the reference signal, and generate a fine-tuning voltage, wherein the fine-tuning voltage indicates a phase difference between the reference signal and the buffered divided signal;
- and
- a voltage-controlled oscillator (VCO), which is configured to adjust the output signal based on the coarse-tuning voltage and the fine-tuning voltage.
6 more elements
A phase-locked loop (PLL) comprising:
- a frequency detector, which is configured to receive a reference signal and an output signal, and generate a coarse-tuning voltage, wherein the coarse-tuning voltage indicates a frequency difference between the reference signal and the output signal;
- a sub-sampling phase detector (SSPD), which is configured to sub-sample the output signal using the reference signal, and generate a fine-tuning voltage, wherein:
- the SSPD comprises a first switch, a first capacitor, a unit-gain buffer, a non-overlap generator, a second switch, and a second capacitor;
- the first switch is configured to sub-sample the output signal onto the first capacitor providing a sampled voltage, wherein the first switch is controlled by the reference signal;
- the unit-gain buffer is configured to receive the sampled voltage and generate a buffered sampled voltage;
- the non-overlap generator is configured to generate a non-overlap clock based on the reference signal, wherein the non-overlap clock and the reference signal have a same frequency, and are never overlapped with each other;
- the second switch is configured to sample the buffered sampled voltage onto the second capacitor providing the fine-tuning voltage, wherein the second switch is controlled by the non-overlap clock;
- and
- the fine-tuning voltage indicates a phase difference between the reference signal and the output signal;
- and
- a voltage-controlled oscillator (VCO), which is configured to adjust the output signal based on the coarse-tuning voltage and the fine-tuning voltage.
8 more elements
A phase-locked loop (PLL) comprising:
- a frequency divider, which is configured to receive an output signal and generate a divided signal by frequency dividing the output signal with a frequency divide ratio;
- a frequency detector, which is configured to receive a reference signal and the divided signal, and generate a coarse-tuning voltage, wherein the coarse-tuning voltage indicates a frequency difference between the reference signal and the divided signal;
- a sub-sampling phase detector (SSPD), which is configured to sub-sample the divided signal using the reference signal, and generate a fine-tuning voltage, wherein:
- the SSPD comprises a first switch, a first capacitor, a unit-gain buffer, a non-overlap generator, a second switch, and a second capacitor;
- the first switch is configured to sub-sample the divided signal onto the first capacitor providing a sampled voltage, wherein the first switch is controlled by the reference signal;
- the unit-gain buffer is configured to receive the sampled voltage and generate a buffered sampled voltage;
- the non-overlap generator is configured to generate a non-overlap clock based on the reference signal, wherein the non-overlap clock and the reference signal have a same frequency, and are never overlapped with each other;
- the second switch is configured to sample the buffered sampled voltage onto the second capacitor providing the fine-tuning voltage, wherein the second switch is controlled by the non-overlap clock;
- and
- the fine-tuning voltage indicates a phase difference between the reference signal and the divided signal;
- and
- a voltage-controlled oscillator (VCO), which is configured to adjust the output signal based on the coarse-tuning voltage and the fine-tuning voltage.
9 more elements
A phase-locked loop (PLL) comprising:
- a frequency detector, which is configured to receive a reference signal and an output signal, and to generate a coarse-tuning voltage, wherein the coarse-tuning voltage indicates a frequency difference between the reference signal and the output signal;
- a controlled slope buffer configured to receive the output signal and generate a buffered signal, wherein:
- the buffered signal and the output signal have a same frequency;
- and
- the buffered signal has a higher slope and shorter rising time than the output signal;
- a sub-sampling phase detector (SSPD), which is configured to sub-sample the buffered signal using the reference signal, and to generate a fine-tuning voltage, wherein the fine-tuning voltage indicates a phase difference between the reference signal and the buffered signal;
- and
- a voltage-controlled oscillator (VCO), which is configured to adjust the output signal based on the coarse-tuning voltage and the fine-tuning voltage.
5 more elements
Dependencies are inferred from the claim text.