Hierarchical partial reconfiguration for programmable integrated circuits

A method, comprising:

• implementing a first circuitry within a static region of a programmable integrated circuit, the first circuitry specified by a first partial bitstream;
• implementing a second circuitry within a partial reconfiguration container region of the programmable integrated circuit, the second circuitry specified by a second partial bitstream;
• and
• implementing a third circuitry within a first partial reconfiguration region contained within the partial reconfiguration container region and a fourth circuitry within a second partial reconfiguration region contained within the partial reconfiguration container region, wherein the third circuitry is specified by a third partial bitstream and the fourth circuitry is specified by a fourth partial bitstream.

An integrated circuit, comprising:

• a static region including first programmable circuitry configured to implement an interface with an external device;
• and
• a partial reconfiguration container region coupled to the static region that implements an interface to the static region using second programmable circuitry;
• wherein the partial reconfiguration container region includes a first plurality of partial reconfiguration regions, wherein at least one of first plurality of partial reconfiguration regions is coupled to the partial reconfiguration container region.