Dead Time Control Circuit for a Level Shifter

A dead time control circuit configured to generate, from an input square wave signal, a high side (HS) timing control signal and a low side (LS) timing control signal for respective control of a high side (HS) device and a low side (LS) device arranged in a stacked configuration, the dead time control circuit comprising:

• a first processing path comprising respective two edge delay circuits arranged in series connection, each edge delay circuit of the first processing path configured to delay a respective one of a rising edge and a falling edge of the input square wave signal to generate therefrom a first edge adjusted pulse signal of the HS timing control signal;
• and
• a second processing path comprising respective two edge delay circuits arranged in series connection, each edge delay circuit of the second processing path configured to delay a respective one of the rising edge and the falling edge of the input square wave signal independently from the first processing path to generate therefrom a second edge adjusted pulse signal of the LS timing control signal that is substantially out of phase with respect to the first edge adjusted pulse signal;
• wherein, for each of the first processing path and the second processing path, an adjustable edge delay provided by each edge delay circuit of the respective two edge delay circuits is based on a respective adjustable charging time of one capacitor by a respective current source to reach a trip point voltage of a respective inverter, and
• wherein the adjustable edge delay is configured to control a timing between the first edge adjusted pulse signal and the second edge adjusted pulse signal in a range from an overlap time to a dead time.

A method for generating, based on an input square wave signal, a high side (HS) timing control signal and a low side (LS) timing control signal for respective control of a high side (HS) device and a low side (LS) device arranged in a stacked configuration, the method comprising:

• processing the input square wave signal through a first processing path, the first processing path comprising respective two edge delay circuits arranged in series connection, each edge delay circuit of the first processing path configured to delay a respective one of a rising edge and a falling edge of the input square wave signal to generate therefrom a first edge adjusted pulse signal of the HS timing control signal;
• and
• processing the input square wave signal through a second processing path, the second processing path comprising respective two edge delay circuits arranged in series connection, each edge delay circuit of the second processing path configured to delay a respective one of the rising edge and the falling edge of the input square wave signal independently from the first processing path to generate therefrom a second edge adjusted pulse signal of the LS timing control signal that is substantially out of phase with respect to the first edge adjusted pulse signal;
• and
• based on the processing and based on an adjustable edge delay provided by each of the respective two edge delay circuits of the first and the second processing paths, controlling a timing between the first edge adjusted pulse signal and the second edge adjusted pulse signal in a range from an overlap time to a dead time,
• wherein the adjustable edge delay is based on an adjustable charging time of at least one capacitor by a current source to reach a trip point voltage of an inverter.