US 2020/0028498 A1Published application

Semiconductor device and electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsHajime KIMURA, Yoshiyuki KUROKAWA

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Abstract

A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

Claims19

Dependent claims

A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a first logic circuit, a second logic circuit, a first holding unit, and a second holding unit,
wherein:
each of the first logic circuit and the second logic circuit comprises an input terminal, an output terminal, and a power supply potential input terminal,
the first logic circuit is configured to output an inverted signal of a signal input to the input terminal of the first logic circuit, from the output terminal of the first logic circuit,
the second logic circuit is configured to output an inverted signal of a signal input to the input terminal of the second logic circuit, from the output terminal of the second logic circuit,
each of the first to fourth transistors comprises a first gate and a second gate,
the first holding unit comprises a fifth transistor and a first capacitor,
the second holding unit comprises a sixth transistor and a second capacitor,
the power supply potential input terminal of the first logic circuit is electrically connected to a first terminal of the first transistor and a first terminal of the third transistor,
the power supply potential input terminal of the second logic circuit is electrically connected to a first terminal of the second transistor and a first terminal of the fourth transistor,
the first gate of the first transistor is electrically connected to the first gate of the second transistor,
the first gate of the third transistor is electrically connected to the first gate of the fourth transistor,
a first terminal of the fifth transistor is electrically connected to a first terminal of the first capacitor, the second gate of the first transistor, and the second gate of the fourth transistor, and
a first terminal of the sixth transistor is electrically connected to a first terminal of the second capacitor, the second gate of the second transistor, and the second gate of the third transistor.

11 more elements

A semiconductor device comprising:

a first circuit comprising a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit,
wherein:
each of the first to fourth logic circuits comprises an input terminal, an output terminal, and a power supply potential input terminal,
the first logic circuit is configured to output an inverted signal of a signal input to the input terminal of the first logic circuit, from the output terminal of the first logic circuit,
the second logic circuit is configured to output an inverted signal of a signal input to the input terminal of the second logic circuit, from the output terminal of the second logic circuit,
the third logic circuit is configured to output an inverted signal of a signal input to the input terminal of the third logic circuit, from the output terminal of the third logic circuit,
the fourth logic circuit is configured to output an inverted signal of a signal input to the input terminal of the fourth logic circuit, from the output terminal of the fourth logic circuit,
each of the first to fourth transistors comprises a first gate and a second gate,
the first input terminal is electrically connected to the input terminal of one of the first logic circuit and the third logic circuit,
when the first input terminal is electrically connected to the input terminal of the first logic circuit, the output terminal of the first logic circuit is electrically connected to the input terminal of the third logic circuit, the output terminal of the third logic circuit is electrically connected to the first output terminal, the second input terminal is electrically connected to the input terminal of the second logic circuit, the output terminal of the second logic circuit is electrically connected to the input terminal of the fourth logic circuit, and the output terminal of the fourth logic circuit is electrically connected to the second output terminal,
when the first input terminal is electrically connected to the input terminal of the third logic circuit, the output terminal of the third logic circuit is electrically connected to the input terminal of the first logic circuit, the output terminal of the first logic circuit is electrically connected to the first output terminal, the second input terminal is electrically connected to the input terminal of the fourth logic circuit, the output terminal of the fourth logic circuit is electrically connected to the input terminal of the second logic circuit, and the output terminal of the second logic circuit is electrically connected to the second output terminal,
the power supply potential input terminal of the first logic circuit is electrically connected to a first terminal of the first transistor and a first terminal of the third transistor,
the power supply potential input terminal of the second logic circuit is electrically connected to a first terminal of the second transistor and a first terminal of the fourth transistor,
the first gate of the first transistor is electrically connected to the first gate of the second transistor,
the first gate of the third transistor is electrically connected to the first gate of the fourth transistor,
the first circuit is configured to turn on the first transistor and the second transistor and turn off the third transistor and the fourth transistor, or turn off the first transistor and the second transistor and turn on the third transistor and the fourth transistor, in response to a first signal input to the third input terminal, and
the first circuit is configured to change an input/output time from input of a signal to the first input terminal to output of the signal from the first output terminal and an input/output time from input of a signal to the second input terminal to output of the signal from the second output terminal, in response to a potential of the second gate of each of the first to fourth transistors.

14 more elements

A semiconductor device comprising:

a first circuit comprising a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a first switch, a second switch, a third switch, a fourth switch, a first logic circuit, a second logic circuit, a third logic circuit, a fourth logic circuit, a first load circuit, and a second load circuit,
wherein:
each of the first to fourth logic circuits comprises an input terminal, an output terminal, and a power supply potential input terminal,
the first logic circuit is configured to output an inverted signal of a signal input to the input terminal of the first logic circuit, from the output terminal of the first logic circuit,
the second logic circuit is configured to output an inverted signal of a signal input to the input terminal of the second logic circuit, from the output terminal of the second logic circuit,
the third logic circuit is configured to output an inverted signal of a signal input to the input terminal of the third logic circuit, from the output terminal of the third logic circuit,
the fourth logic circuit is configured to output an inverted signal of a signal input to the input terminal of the fourth logic circuit, from the output terminal of the fourth logic circuit,
the first input terminal is electrically connected to the input terminal of one of the first logic circuit and the third logic circuit,
when the first input terminal is electrically connected to the input terminal of the first logic circuit, the output terminal of the first logic circuit is electrically connected to the input terminal of the third logic circuit, the output terminal of the third logic circuit is electrically connected to the first output terminal, the second input terminal is electrically connected to the input terminal of the second logic circuit, the output terminal of the second logic circuit is electrically connected to the input terminal of the fourth logic circuit, and the output terminal of the fourth logic circuit is electrically connected to the second output terminal,
when the first input terminal is electrically connected to the input terminal of the third logic circuit, the output terminal of the third logic circuit is electrically connected to the input terminal of the first logic circuit, the output terminal of the first logic circuit is electrically connected to the first output terminal, the second input terminal is electrically connected to the input terminal of the fourth logic circuit, the output terminal of the fourth logic circuit is electrically connected to the input terminal of the second logic circuit, and the output terminal of the second logic circuit is electrically connected to the second output terminal,
the power supply potential input terminal of the first logic circuit is electrically connected to a first terminal of the first switch and a first terminal of the third switch,
the power supply potential input terminal of the second logic circuit is electrically connected to a first terminal of the second switch and a first terminal of the fourth switch,
a control terminal of the first switch is electrically connected to a control terminal of the second switch,
a control terminal of the third switch is electrically connected to a control terminal of the fourth switch,
a first terminal of the first load circuit is electrically connected to a second terminal of the first switch and a second terminal of the fourth switch,
a first terminal of the second load circuit is electrically connected to a second terminal of the second switch and a second terminal of the third switch,
the first circuit is configured to turn on the first switch and the second switch and turn off the third switch and the fourth switch, or turn off the first switch and the second switch and turn on the third switch and the fourth switch, in response to a first signal input to the third input terminal, and
the first circuit is configured to change an input/output time from input of a signal to the first input terminal to output of the signal from the first output terminal and an input/output time from input of a signal to the second input terminal to output of the signal from the second output terminal, in response to on/off states of the first to fourth switches, a first resistance between the first terminal and a second terminal of the first load circuit, and a second resistance between the first terminal and a second terminal of the second load circuit.

15 more elements

A semiconductor device comprising:

a first circuit comprising a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a first switch, a second switch, a third switch, a fourth switch, a first logic circuit, a second logic circuit, a third logic circuit, a fourth logic circuit, a first load circuit, a second load circuit, a third load circuit, and a fourth load circuit,
wherein:
each of the first to fourth logic circuits comprises an input terminal, an output terminal, and a power supply potential input terminal,
the first logic circuit is configured to output an inverted signal of a signal input to the input terminal of the first logic circuit, from the output terminal of the first logic circuit,
the second logic circuit is configured to output an inverted signal of a signal input to the input terminal of the second logic circuit, from the output terminal of the second logic circuit,
the third logic circuit is configured to output an inverted signal of a signal input to the input terminal of the third logic circuit, from the output terminal of the third logic circuit,
the fourth logic circuit is configured to output an inverted signal of a signal input to the input terminal of the fourth logic circuit, from the output terminal of the fourth logic circuit,
the first input terminal is electrically connected to the input terminal of one of the first logic circuit and the third logic circuit,
when the first input terminal is electrically connected to the input terminal of the first logic circuit, the output terminal of the first logic circuit is electrically connected to the input terminal of the third logic circuit, the output terminal of the third logic circuit is electrically connected to the first output terminal, the second input terminal is electrically connected to the input terminal of the second logic circuit, the output terminal of the second logic circuit is electrically connected to the input terminal of the fourth logic circuit, and the output terminal of the fourth logic circuit is electrically connected to the second output terminal,
when the first input terminal is electrically connected to the input terminal of the third logic circuit, the output terminal of the third logic circuit is electrically connected to the input terminal of the first logic circuit, the output terminal of the first logic circuit is electrically connected to the first output terminal, the second input terminal is electrically connected to the input terminal of the fourth logic circuit, the output terminal of the fourth logic circuit is electrically connected to the input terminal of the second logic circuit, and the output terminal of the second logic circuit is electrically connected to the second output terminal,
the power supply potential input terminal of the first logic circuit is electrically connected to a first terminal of the first switch and a first terminal of the third switch,
the power supply potential input terminal of the second logic circuit is electrically connected to a first terminal of the second switch and a first terminal of the fourth switch,
a control terminal of the first switch is electrically connected to a control terminal of the second switch,
a control terminal of the third switch is electrically connected to a control terminal of the fourth switch,
a first terminal of the first load circuit is electrically connected to a second terminal of the first switch,
a first terminal of the second load circuit is electrically connected to a second terminal of the third switch,
a first terminal of the third load circuit is electrically connected to a second terminal of the fourth switch,
a first terminal of the fourth load circuit is electrically connected to a second terminal of the second switch,
the first circuit is configured to turn on the first switch and the second switch and turn off the third switch and the fourth switch, or turn off the first switch and the second switch and turn on the third switch and the fourth switch, in response to a first signal input to the third input terminal, and
the first circuit is configured to change an input/output time from input of a signal to the first input terminal to output of the signal from the first output terminal and an input/output time from input of a signal to the second input terminal to output of the signal from the second output terminal, in response to on/off states of the first to fourth switches, a first resistance between the first terminal and a second terminal of the first load circuit, a second resistance between the first terminal and a second terminal of the second load circuit, a third resistance between the first terminal and a second terminal of the third load circuit, and a fourth resistance between the first terminal and a second terminal of the fourth load circuit.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/511,215Filed 15 Jul 2019
Priority: JP 2018-13683920 Jul 2018
Published: 23 Jan 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
H03K 3/037
By the use of logic circuits, with internal or external positive feedback: bistable circuits
G06N 3/04
Neural networks: architecture, e.g. interconnection topology
G06N 3/0442
Recurrent networks, e.g. Hopfield networks: characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]