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US 2020/0028495 A1Published application
High-speed low-power level-shifting clock buffer
AssigneeQUALCOMM Incorporated
InventorTongyu SONG
Life of this patent
Estimating the term…
Abstract
A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.
Claims20
A level-shifting buffer, comprising:
- a first transistor configured to switch on responsive to an assertion of a complement input signal to discharge a pull-down node coupled to a terminal of the first transistor;
- a current mirror configured to charge an internal node in response to a discharge of a current mirror terminal;
- a first switch transistor configured to switch off subsequent to an expiration of a delay following a discharge of an output signal, wherein the first switch transistor is coupled between the pull-down node and the current mirror terminal;
- a second transistor configured to discharge the internal node responsive to an assertion of an input signal to a first power supply voltage, wherein the complement input signal is a complement of the input signal;
- and
- an inverter configured to invert a voltage of the internal node to form the output signal, wherein the inverter is powered by a second power supply voltage that is greater than the first power supply voltage.
3 more elements
A method of level-shifting an input signal to form an output signal, comprising:
- conducting an input current for a current mirror responsive to an assertion of a complement input signal, wherein the complement input signal is a complement of the input signal;
- mirroring the input current through the current mirror to form a mirrored current;
- charging an internal node with the mirrored current;
- discharging the output signal responsive to the charging of the internal node;
- switching off the input current responsive to an expiration of a delay after the discharging of the output signal;
- discharging the internal node responsive to an assertion of the input signal to a first power supply voltage;
- and
- asserting the output signal to a second power supply voltage responsive to the discharging of the internal node, wherein the second power supply voltage is greater than the first power supply voltage.
5 more elements
A level-shifting buffer, comprising:
- a first transistor configured to switch on responsive to an assertion of a complement input signal to discharge a pull-down node coupled to a terminal of the first transistor;
- a current mirror configured to charge an internal node in response to a discharge of a current mirror terminal;
- a second transistor configured to discharge the internal node responsive to an assertion of an input signal to a first power supply voltage, wherein the complement input signal is a complement of the input signal;
- a first inverter configured to invert a voltage of the internal node to form an output signal, wherein the first inverter is powered by a second power supply voltage that is greater than the first power supply voltage;
- and
- means for controlling an input current for the current mirror to conduct through the first transistor during a delay period starting with the assertion of the complement input signal and for shutting off the input current following an expiration of the delay period.
3 more elements
Dependencies are inferred from the claim text.